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<filename>Itautec-Servidor_Itautec-Intel-Linux-Platform.20130418.xml</filename>

<title>SPEC CPU2006 Software OS and BIOS tuning Descriptions for Servidor Itautec Intel-based systems</title>

<firmware>
 <![CDATA[ 
<dl>

 <dt><b>Platform settings</b></dt>
 <dd>One or more of the following settings may have been set.  If so, the "General Notes" 
 section of the report will say so; and you can read below to find out more about what 
 these settings mean.</dd>

 <dt><b>Hardware Prefetch:</b></dt> 
 <dd>
 This BIOS option allows the enabling/disabling of a processor mechanism to                 
 prefetch data into the cache according to a pattern-recognition algorithm.
 In some cases, setting this option to Disabled may improve
 performance. Users should only disable this option 
 after performing application benchmarking to verify improved
 performance in their environment.
 </dd>

 <dt><b>Adjacent Cache Line Prefetch:</b></dt> 
 <dd>
 This BIOS option allows the enabling/disabling of a processor mechanism to                 
 fetch the adjacent cache line within a 128-byte sector that contains 
 the data needed due to a cache line miss.
 In some cases, setting this option to Disabled may improve
 performance. Users should only disable this option 
 after performing application benchmarking to verify improved
 performance in their environment.
 </dd>

 <dt><b>DCU prefetcher:</b></dt>
 <dd>Detects multiple reading from a single cache line for a determined period of time 
 and decides to load the following line in the L1 cache.
 In some cases, setting this option to Disabled may improve
 performance. Users should only disable this option 
 after performing application benchmarking to verify improved
 performance in their environment.
 </dd>
 
<dt><b>Data Reuse:</b></dt> 
 <dd>
 Enabling this BIOS option reduces the frequency of L3 cache updates from L1.
 This may improve performance by reducing the internal bandwidth consumed 
 by constantly updating L1 cache lines in L3.
 Since this results in more fetches to main memory,                
 setting this option to Disabled may improve performance in some cases.
 In some cases, setting this option to Disabled may improve
 performance. Users should only disable this option 
 after performing application benchmarking to verify improved
 performance in their environment.
 </dd>
 <dt><b>High Bandwidth:</b></dt> 
 <dd>
 Enabling this option allows the chipset to defer memory transactions and 
 process them out of order for optimal performance. 
 </dd>
 <dt><b>
 Intel Hyper Threading Technology:</b></dt>
 <dd>
 Set to Enabled to use the processor`s Intel Hyper Threading Technoloy feature. 
 With HT Technology, the operating system can  execute two threads in parallel 
 within each processor core. The options are Enabled and Dissabled.
 </dd>
 <dt><b>Node Interleaving:</b></dt> 
 <dd>
 This BIOS option allows the enabling/disabling of memory interleaving across 
 CPU nodes. When disabled, each CPU chip can only access memory within its own node. 
 </dd>
</dl>
  ]]> 
</firmware>
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