From d280c3a4a6ea0b3b9bf03bd4d4bd36b7e763287e Mon Sep 17 00:00:00 2001
From: lixianglai <lixianglai@loongson.cn>
Date: Wed, 23 Aug 2023 07:10:25 -0400
Subject: [PATCH 28/28] Fixed the issue where qemu specifies the boot order

Fixed the issue that the device path of bootorder
in the generated fw_cfg was abnormal because the
PCIeHost device did not initialize the memory space
of sysbus, which caused the QEMU boot order to not
take effect.

Change-Id: Ifde4c8b8432c5c8748c1b38a3c33bafef4f24083
Signed-off-by: lixianglai <lixianglai@loongson.cn>
---
 hw/loongarch/larch_3a.c      | 14 --------------
 hw/loongarch/ls7a_nb.c       | 28 ++++++++++++++++++++++++++--
 include/hw/loongarch/larch.h |  6 ++++++
 include/hw/loongarch/ls7a.h  |  2 ++
 4 files changed, 34 insertions(+), 16 deletions(-)

diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c
index 2affc5048..1a4e982b7 100644
--- a/hw/loongarch/larch_3a.c
+++ b/hw/loongarch/larch_3a.c
@@ -86,12 +86,6 @@
 
 #define TARGET_REALPAGE_MASK (TARGET_PAGE_MASK << 2)
 
-#ifdef CONFIG_KVM
-#define LS_ISA_IO_SIZE          0x02000000
-#else
-#define LS_ISA_IO_SIZE          0x00010000
-#endif
-
 #ifdef CONFIG_KVM
 #define align(x) (((x) + 63) & ~63)
 #else
@@ -1618,8 +1612,6 @@ static void ls3a5k_init(MachineState *args)
     ram_addr_t ram_size = args->ram_size;
     MemoryRegion *address_space_mem = get_system_memory();
     ram_addr_t offset = 0;
-    MemoryRegion *isa_io = g_new(MemoryRegion, 1);
-    MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
     MachineState *machine = args;
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     LoongarchMachineState *lsms = LoongarchMACHINE(machine);
@@ -1799,12 +1791,6 @@ static void ls3a5k_init(MachineState *args)
                                     &machine->device_memory->mr);
     }
 
-    memory_region_init_alias(isa_io, NULL, "isa-io",
-                             get_system_io(), 0, LS_ISA_IO_SIZE);
-    memory_region_init(isa_mem, NULL, "isa-mem", PCIE_MEMORY_SIZE);
-    memory_region_add_subregion(get_system_memory(), lsmc->isa_io_base, isa_io);
-    memory_region_add_subregion(get_system_memory(), PCIE_MEMORY_BASE, isa_mem);
-
     if (!strcmp(lsmc->bridge_name, "ls7a")) {
         /*Initialize the 7A IO interrupt subsystem*/
         DeviceState *ls7a_dev;
diff --git a/hw/loongarch/ls7a_nb.c b/hw/loongarch/ls7a_nb.c
index 5a231e6f0..f11b855a7 100644
--- a/hw/loongarch/ls7a_nb.c
+++ b/hw/loongarch/ls7a_nb.c
@@ -162,17 +162,41 @@ static PCIBus *pci_ls7a_init(MachineState *machine, DeviceState *dev,
 {
     LoongarchMachineState *lsms = LoongarchMACHINE(machine);
     LoongarchMachineClass *lsmc = LoongarchMACHINE_GET_CLASS(lsms);
+    LS7APCIEHost *pciehost = LS7A_PCIE_HOST_BRIDGE(dev);
     PCIExpressHost *e;
+    SysBusDevice *sysbus;
     PCIHostState *phb;
+    MemoryRegion *mmio_alias;
 
     e = PCIE_HOST_BRIDGE(dev);
+    sysbus = SYS_BUS_DEVICE(e);
     phb = PCI_HOST_BRIDGE(e);
+
+    sysbus_init_mmio(sysbus, &e->mmio);
+
+    memory_region_init(&pciehost->io_mmio, OBJECT(pciehost),
+                       "pciehost-mmio", UINT64_MAX);
+    sysbus_init_mmio(sysbus, &pciehost->io_mmio);
+    mmio_alias = g_new0(MemoryRegion, 1);
+    memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
+                             &pciehost->io_mmio, PCIE_MEMORY_BASE,
+                             PCIE_MEMORY_SIZE);
+    memory_region_add_subregion(get_system_memory(),
+                                PCIE_MEMORY_BASE, mmio_alias);
+
+    memory_region_init(&pciehost->io_ioport, OBJECT(pciehost),
+                       "pciehost-ioport", LS_ISA_IO_SIZE);
+    sysbus_init_mmio(sysbus, &pciehost->io_ioport);
+
+    sysbus_mmio_map(sysbus, 2, LS3A5K_ISA_IO_BASE);
+
+
     phb->bus = pci_register_root_bus(dev, "pcie.0", pci_ls7a_set_irq,
                                      pci_ls7a_map_irq, pic,
-                                     get_system_memory(), get_system_io(),
+                                     &pciehost->io_mmio, &pciehost->io_ioport,
                                      (1 << 3), 128, TYPE_PCIE_BUS);
+    /*update pcie config memory*/
     pcie_host_mmcfg_update(e, true, lsmc->pciecfg_base, LS_PCIECFG_SIZE);
-    DPRINTF("------ %d\n", __LINE__);
 
     pci_bus_set_route_irq_fn(phb->bus, ls7a_route_intx_pin_to_irq);
 
diff --git a/include/hw/loongarch/larch.h b/include/hw/loongarch/larch.h
index b8f28e330..3f4fdd946 100644
--- a/include/hw/loongarch/larch.h
+++ b/include/hw/loongarch/larch.h
@@ -40,6 +40,12 @@
 #define LOONGARCH_HOTPLUG_MEM_ALIGN (1ULL << 28)
 #define LOONGARCH_MAX_RAM_SLOTS     10
 
+#ifdef CONFIG_KVM
+#define LS_ISA_IO_SIZE          0x02000000
+#else
+#define LS_ISA_IO_SIZE          0x00010000
+#endif
+
 /* Memory types: */
 #define SYSTEM_RAM              1
 #define SYSTEM_RAM_RESERVED     2
diff --git a/include/hw/loongarch/ls7a.h b/include/hw/loongarch/ls7a.h
index 63a070296..05edee603 100644
--- a/include/hw/loongarch/ls7a.h
+++ b/include/hw/loongarch/ls7a.h
@@ -121,6 +121,8 @@
 typedef struct LS7APCIState LS7APCIState;
 typedef struct LS7APCIEHost {
     PCIExpressHost parent_obj;
+    MemoryRegion io_ioport;
+    MemoryRegion io_mmio;
     LS7APCIState *pci_dev;
 } LS7APCIEHost;
 
-- 
2.43.5