; AVS enable
; OTP data is stored in SM0~SM2 from GPP1
; SVC_REV is stored in SM3
;
LOAD_SM_VAL: SM4 0x97DFFFFF ;# Set VDD to 1100mV by default
;
TEST_SM_AND_BRANCH: SM3 0x0000000F 0x2 < AVSR	;use default value if SVC_REV<2
;
; read SVC_600Mhz in OTP Data[55:50] = (D1>>18 & 0x3F)
RSHIFT_SM_VAL: SM1 18
ADD_SM_VAL: SM1 0xd	;base voltage is 0.898V(0xd), AVS=OTP+0xd
AND_SM_VAL: SM1 0x3F
; set AVS to register
LOAD_SM_VAL: SM4 0x9000FFFF
LSHIFT_SM_VAL: SM1 16
OR_SM_SM: SM4 SM1
LSHIFT_SM_VAL: SM1 6
OR_SM_SM: SM4 SM1
;
; perform AVS reset
LABEL: AVSR
STORE_SM_ADDR: SM4 0xC0011500
AND_VAL: 0xC0011500 0x1FFFFFFF	;# release AVS reset
OR_VAL: 0xC0011500 0x50000000	;# Enable AVS
DELAY: 0x000186A0               ;# Delay 100ms for AVS voltage wake up
; Switch all clocks to REFCLOCK
WRITE: 0XC0013010 0x00000000
WRITE: 0XC0018010 0x00000000
; TBG-A: SE vco_div 0x0,
; DIFF vco_div 0x1, vco_range 0xd
; tbg_N 0x48 KVCO = 2400 MHz
WRITE: 0xC0013204 0x00C00091
WRITE: 0xC0013204 0x00C00121
WRITE: 0xC0013220 0x08030803
WRITE: 0xC0013208 0x94011401
WRITE: 0xC0013230 0x00020002
WRITE: 0xC0013208 0x94011401
WRITE: 0xC001320C 0x53E556E6
WRITE: 0xC0013210 0x014A014D
WRITE: 0xC001320C 0x53E556E6
WRITE: 0xC0013204 0x00C00120
WRITE: 0xC0013208 0x94011401
WAIT_FOR_BIT_SET: 0xC0013208 0x80008000 0x00100000
DELAY: 0x00000100
; TBG-B: SE vco_div 0x1,
; DIFF vco_div 0x1, vco_range 0xb
; tbg_N 0x3c KVCO = 2000 MHz
WRITE: 0xC0013204 0x00C10120
WRITE: 0xC0013204 0x00F10120
WRITE: 0xC0013220 0x08030803
WRITE: 0xC0013208 0x14019401
WRITE: 0xC0013230 0x00020002
WRITE: 0xC0013208 0x14019401
WRITE: 0xC001320C 0x56E556E6
WRITE: 0xC0013210 0x014B014D
WRITE: 0xC001320C 0x56E656E6
WRITE: 0xC0013204 0x00F00120
WRITE: 0xC0013208 0x14019401
WAIT_FOR_BIT_SET: 0xC0013208 0x80008000 0x00100000
DELAY: 0x00000100
; Set clocks to 600/600 preset
WRITE: 0xC0013014 0x00000000
WRITE: 0xC0013004 0x2326202A
WRITE: 0xC0013008 0x1A09AAA9
WRITE: 0xC001300C 0x208B3484
WRITE: 0xC0013000 0x0333C0FE
WRITE: 0xC0018014 0x00180000
WRITE: 0xC0018004 0x053154C8
WRITE: 0xC0018008 0x00300880
WRITE: 0xC001800C 0x00000940
WRITE: 0xC0018000 0x003F8F40
WRITE: 0xC0013210 0x014B014D
; Switch all clocks to back dividers
WRITE: 0xC0013010 0x00009FFF
WRITE: 0xC0018010 0x000007AA