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From b497814a4c2bdb5d229b29dc862f439ada748fc3 Mon Sep 17 00:00:00 2001
From: chenyangping <[email protected]>
Date: Tue, 26 Sep 2023 10:00:20 +0800
Subject: [PATCH 11/12] add PCIe device isolation function on ft2004 board,
isolation rc and its to non root cell, so all PCIe devices show in non root
cell [KEYWORDS] none [TO SOLVE] none [TEST SUGGESTION] none [SUBMIT BY]
chenyangping [REVIEW BY] chenyangping [TEST BY] chenyangping
---
configs/arm64/dts/ft2004-pcie-linux.dts | 120 ++++++++++
configs/arm64/ft2004-pcie-linux.c | 179 ++++++++++++++
configs/arm64/ft2004-pcie-main.c | 298 ++++++++++++++++++++++++
3 files changed, 597 insertions(+)
create mode 100644 configs/arm64/dts/ft2004-pcie-linux.dts
create mode 100644 configs/arm64/ft2004-pcie-linux.c
create mode 100644 configs/arm64/ft2004-pcie-main.c
diff --git a/configs/arm64/dts/ft2004-pcie-linux.dts b/configs/arm64/dts/ft2004-pcie-linux.dts
new file mode 100644
index 00000000..48c9f456
--- /dev/null
+++ b/configs/arm64/dts/ft2004-pcie-linux.dts
@@ -0,0 +1,120 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "jailhouse,cell";
+ };
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x00>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 0x00 0x29980000 0x00 0x80000 0x00 0x29c00000 0x00 0x10000 0x00 0x29c10000 0x00 0x10000 0x00 0x29c20000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+
+ gic-its@29920000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x00 0x29920000 0x00 0x20000>;
+ phandle = <0x05>;
+ };
+
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+ uart@28000000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x06 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+
+ pcie {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x05>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x1c 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x1d 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x1e 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x1f 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ };
+ };
+};
diff --git a/configs/arm64/ft2004-pcie-linux.c b/configs/arm64/ft2004-pcie-linux.c
new file mode 100644
index 00000000..72d6dbdc
--- /dev/null
+++ b/configs/arm64/ft2004-pcie-linux.c
@@ -0,0 +1,179 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[15];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[0];
+ struct jailhouse_pci_capability pci_caps[0];
+} __attribute__((packed)) config = {
+ .cell =
+ {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "linux",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .num_pci_caps = ARRAY_SIZE(config.pci_caps),
+ .vpci_irq_base = 101,
+ .console =
+ {
+ .address = 0x28000000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags =
+ JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {0b0001},
+
+ .irqchips =
+ {
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap =
+ {
+ 1 << (38 - 32),
+ 0,
+ 0,
+ 0xffffffff,
+ },
+ },
+ },
+
+ .mem_regions = {
+ /* UART */ {
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */
+ {
+ .phys_start = 0x92000000,
+ .virt_start = 0,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+
+ /* RAM */
+ {
+ .phys_start = 0x93000000,
+ .virt_start = 0x93000000,
+ .size = 0x1d000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */
+ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ {
+ .phys_start = 0x2a000000,
+ .virt_start = 0x2a000000,
+ .size = 0x1000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* MemRegion: 58300000-583fffff : 0000:06:00.0 */
+ {
+ .phys_start = 0x58300000,
+ .virt_start = 0x1000000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* gic its */
+ {
+ .phys_start = 0x29920000,
+ .virt_start = 0x29920000,
+ .size = 0x20000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe ECAM */
+ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x10000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe IO */
+ {
+ .phys_start = 0x50000000,
+ .virt_start = 0x50000000,
+ .size = 0x8000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem32 */
+ {
+ .phys_start = 0x58000000,
+ .virt_start = 0x58000000,
+ .size = 0x28000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem64 */
+ {
+ .phys_start = 0x1000000000,
+ .virt_start = 0x1000000000,
+ .size = 0x1000000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /*gicr*/
+ {
+ .phys_start = 0x29980000,
+ .virt_start = 0x29980000,
+ .size = 0x80000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /*gicc*/
+ {
+ .phys_start = 0x29c00000,
+ .virt_start = 0x29c00000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /*gich*/
+ {
+ .phys_start = 0x29c10000,
+ .virt_start = 0x29c10000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ },
+
+ .pci_devices =
+ {
+
+ },
+ .pci_caps =
+ {
+
+ },
+};
diff --git a/configs/arm64/ft2004-pcie-main.c b/configs/arm64/ft2004-pcie-main.c
new file mode 100644
index 00000000..13fda789
--- /dev/null
+++ b/configs/arm64/ft2004-pcie-main.c
@@ -0,0 +1,298 @@
+/**
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (C), 2022, Kylinsoft Corporation.
+ *
+ * @author [email protected]
+ * @date 2022.08.05
+ * @brief ft2004 guest linux config file test ivshmem-net
+ * @note
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[25];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[0];
+} __attribute__((packed)) config = {
+ .header =
+ {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory =
+ {
+ .phys_start = 0xb0000000,
+ .size = 0x01000000,
+ },
+ .debug_console =
+ {
+ .address = 0x28001000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags =
+ JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info =
+ {
+ .pci_mmconfig_base = 0x40000000,
+ .pci_mmconfig_end_bus = 6,
+ .pci_is_virtual = 0,
+ .pci_domain = 0,
+
+ .arm =
+ {
+ .gic_version = 3,
+ .gicd_base = 0x29900000,
+ .gicr_base = 0x29980000,
+ .gicc_base = 0x29c00000,
+ .gich_base = 0x29c10000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell =
+ {
+ .name = "ft2004",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 100,
+ },
+ },
+
+ .cpus =
+ {
+ 0xf,
+ },
+
+ .mem_regions =
+ {
+ /* Main memory */
+ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x80000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x2000000000,
+ .virt_start = 0x2000000000,
+ .size = 0x380000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UART 0-3 */
+ {
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x4000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* GPIO 0-1 */
+ {
+ .phys_start = 0x28004000,
+ .virt_start = 0x28004000,
+ .size = 0x2000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* I2C 0-1 */
+ {
+ .phys_start = 0x28006000,
+ .virt_start = 0x28006000,
+ .size = 0x2000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 0 */
+ {
+ .phys_start = 0x2800a000,
+ .virt_start = 0x2800a000,
+ .size = 0x2000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 1 */
+ {
+ .phys_start = 0x28016000,
+ .virt_start = 0x28016000,
+ .size = 0x2000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* SPI 0 */
+ {
+ .phys_start = 0x2800c000,
+ .virt_start = 0x2800c000,
+ .size = 0x1000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* SPI 1 */
+ {
+ .phys_start = 0x28013000,
+ .virt_start = 0x28013000,
+ .size = 0x1000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* QSPI */
+ {
+ .phys_start = 0x28014000,
+ .virt_start = 0x28014000,
+ .size = 0x1000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* HDA */
+ {
+ .phys_start = 0x28206000,
+ .virt_start = 0x28206000,
+ .size = 0x1000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* CAN 0-2 and SDCI*/
+ {
+ .phys_start = 0x28207000,
+ .virt_start = 0x28207000,
+ .size = 0x1000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* ETH0 */
+ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* ETH1 */
+ {
+ .phys_start = 0x28210000,
+ .virt_start = 0x28210000,
+ .size = 0x2000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* Mailbox */
+ {
+ .phys_start = 0x2a000000,
+ .virt_start = 0x2a000000,
+ .size = 0x1000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* SRAM */
+ {
+ .phys_start = 0x2a006000,
+ .virt_start = 0x2a006000,
+ .size = 0x2000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* GIC ITS */
+ {
+ .phys_start = 0x29920000,
+ .virt_start = 0x29920000,
+ .size = 0x20000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe ECAM */
+ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x10000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe IO */
+ {
+ .phys_start = 0x50000000,
+ .virt_start = 0x50000000,
+ .size = 0x8000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem32 */
+ {
+ .phys_start = 0x58000000,
+ .virt_start = 0x58000000,
+ .size = 0x28000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem64 */
+ {
+ .phys_start = 0x1000000000,
+ .virt_start = 0x1000000000,
+ .size = 0x1000000000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /*gicd*/
+ {
+ .phys_start = 0x29900000,
+ .virt_start = 0x29900000,
+ .size = 0x20000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /*gicr*/
+ {
+ .phys_start = 0x29980000,
+ .virt_start = 0x29980000,
+ .size = 0x80000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /*gicc*/
+ {
+ .phys_start = 0x29c00000,
+ .virt_start = 0x29c00000,
+ .size = 0x10000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ /*gich*/
+ {
+ .phys_start = 0x29c10000,
+ .virt_start = 0x29c10000,
+ .size = 0x20000,
+ .flags =
+ JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips =
+ {
+ /* GIC */
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap =
+ {
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ },
+ },
+ },
+ .pci_devices =
+ {
+
+ },
+};
--
2.25.1
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