代码拉取完成，页面将自动刷新
From b5d0e28235d32deefe3b02672cedfb63582c83f7 Mon Sep 17 00:00:00 2001
From: huanglei <[email protected]>
Date: Tue, 27 Dec 2022 19:03:47 -0800
Subject: [PATCH 02/12] add phytium ft2004,d2000,e2000 dts
---
configs/arm64/dts/phytium/e2000-cluster0.dts | 168 ++++++
.../arm64/dts/phytium/ft2004-AMA0-ivshmem.dts | 148 +++++
.../arm64/dts/phytium/ft2004-AMA0-uart.dts | 111 ++++
configs/arm64/dts/phytium/ft2004-AMA0.dts | 148 +++++
.../arm64/dts/phytium/ft2004-AMA1-ivshmem.dts | 148 +++++
.../arm64/dts/phytium/ft2004-AMA1-uart.dts | 111 ++++
.../arm64/dts/phytium/ft2004-guest-eth.dts | 131 +++++
configs/arm64/dts/phytium/ft2004-main-eth.dts | 441 +++++++++++++++
configs/arm64/dts/phytium/ft2004.dts | 506 ++++++++++++++++++
configs/arm64/dts/phytium/ftd2000-AMA0.dts | 111 ++++
configs/arm64/dts/phytium/ftd2000-AMA1.dts | 111 ++++
11 files changed, 2134 insertions(+)
create mode 100644 configs/arm64/dts/phytium/e2000-cluster0.dts
create mode 100644 configs/arm64/dts/phytium/ft2004-AMA0-ivshmem.dts
create mode 100644 configs/arm64/dts/phytium/ft2004-AMA0-uart.dts
create mode 100644 configs/arm64/dts/phytium/ft2004-AMA0.dts
create mode 100644 configs/arm64/dts/phytium/ft2004-AMA1-ivshmem.dts
create mode 100644 configs/arm64/dts/phytium/ft2004-AMA1-uart.dts
create mode 100644 configs/arm64/dts/phytium/ft2004-guest-eth.dts
create mode 100644 configs/arm64/dts/phytium/ft2004-main-eth.dts
create mode 100644 configs/arm64/dts/phytium/ft2004.dts
create mode 100644 configs/arm64/dts/phytium/ftd2000-AMA0.dts
create mode 100644 configs/arm64/dts/phytium/ftd2000-AMA1.dts
diff --git a/configs/arm64/dts/phytium/e2000-cluster0.dts b/configs/arm64/dts/phytium/e2000-cluster0.dts
new file mode 100644
index 00000000..d9337c8d
--- /dev/null
+++ b/configs/arm64/dts/phytium/e2000-cluster0.dts
@@ -0,0 +1,168 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,e2000q";
+ interrupt-parent = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "E2000Q TESTA DDR4 Board";
+
+ aliases {
+ serial1 = "/soc/uart@2800d000";
+ };
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x6>;
+ };
+
+ core1 {
+ cpu = <0x7>;
+ };
+ };
+
+ };
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "phytium,ftc310", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clocks = <0xa 0x0>;
+ phandle = <0x6>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "phytium,ftc310", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ clocks = <0xa 0x1>;
+ phandle = <0x7>;
+ };
+ };
+
+ interrupt-controller@30800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x3>;
+ interrupt-controller;
+ reg = <0x0 0x30800000 0x0 0x20000 0x0 0x30880000 0x0 0x80000 0x0 0x30840000 0x0 0x10000 0x0 0x30850000 0x0 0x10000 0x0 0x30860000 0x0 0x10000>;
+ phandle = <0x1>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
+ clock-frequency = <0x2faf080>;
+ };
+
+ clocks {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0xc>;
+ };
+
+ clk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x5f5e100>;
+ phandle = <0xd>;
+ };
+
+ clk200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0xbebc200>;
+ phandle = <0x10>;
+ };
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x11>;
+ };
+
+ clk300mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x11e1a300>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0xf>;
+ };
+
+ clk1200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x47868c00>;
+ phandle = <0xb>;
+ };
+ };
+
+ pci@30000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0x0 0x0>;
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x66 0x1>;
+ reg = <0x0 0x30000000 0x0 0x100000>;
+ ranges = <0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x10000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ dma-coherent;
+ ranges;
+
+ uart@2800d000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2800d000 0x0 0x1000>;
+ interrupts = <0x0 0x54 0x4>;
+ clocks = <0xd 0xd>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "okay";
+ };
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004-AMA0-ivshmem.dts b/configs/arm64/dts/phytium/ft2004-AMA0-ivshmem.dts
new file mode 100644
index 00000000..284e8ab6
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004-AMA0-ivshmem.dts
@@ -0,0 +1,148 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <&gic>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ gic: interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ // #address-cells = <0x02>;
+ // #size-cells = <0x02>;
+ // ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 >,
+ <0x00 0x29980000 0x00 0x80000>,
+ < 0x00 0x29c00000 0x00 0x10000>,
+ < 0x00 0x29c10000 0x00 0x10000>,
+ < 0x00 0x29c20000 0x00 0x10000>;
+ //interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+ };
+
+
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+pci@30000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 2 &gic GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 3 &gic GIC_SPI 105 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 4 &gic GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x0 0x30000000 0x0 0x100000>;
+ ranges =
+ <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28000000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x06 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+ /* pcie {
+ compatible = "pci-host-ecam-generic";
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x05>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x1c 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x1d 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x1e 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x1f 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ };*/
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004-AMA0-uart.dts b/configs/arm64/dts/phytium/ft2004-AMA0-uart.dts
new file mode 100644
index 00000000..228c127a
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004-AMA0-uart.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 0x00 0x29980000 0x00 0x80000 0x00 0x29c00000 0x00 0x10000 0x00 0x29c10000 0x00 0x10000 0x00 0x29c20000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28001000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x07 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004-AMA0.dts b/configs/arm64/dts/phytium/ft2004-AMA0.dts
new file mode 100644
index 00000000..284e8ab6
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004-AMA0.dts
@@ -0,0 +1,148 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <&gic>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ gic: interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ // #address-cells = <0x02>;
+ // #size-cells = <0x02>;
+ // ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 >,
+ <0x00 0x29980000 0x00 0x80000>,
+ < 0x00 0x29c00000 0x00 0x10000>,
+ < 0x00 0x29c10000 0x00 0x10000>,
+ < 0x00 0x29c20000 0x00 0x10000>;
+ //interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+ };
+
+
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+pci@30000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 2 &gic GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 3 &gic GIC_SPI 105 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 4 &gic GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x0 0x30000000 0x0 0x100000>;
+ ranges =
+ <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28000000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x06 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+ /* pcie {
+ compatible = "pci-host-ecam-generic";
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x05>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x1c 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x1d 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x1e 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x1f 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ };*/
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004-AMA1-ivshmem.dts b/configs/arm64/dts/phytium/ft2004-AMA1-ivshmem.dts
new file mode 100644
index 00000000..284e8ab6
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004-AMA1-ivshmem.dts
@@ -0,0 +1,148 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <&gic>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ gic: interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ // #address-cells = <0x02>;
+ // #size-cells = <0x02>;
+ // ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 >,
+ <0x00 0x29980000 0x00 0x80000>,
+ < 0x00 0x29c00000 0x00 0x10000>,
+ < 0x00 0x29c10000 0x00 0x10000>,
+ < 0x00 0x29c20000 0x00 0x10000>;
+ //interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+ };
+
+
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+pci@30000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 2 &gic GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 3 &gic GIC_SPI 105 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 4 &gic GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x0 0x30000000 0x0 0x100000>;
+ ranges =
+ <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28000000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x06 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+ /* pcie {
+ compatible = "pci-host-ecam-generic";
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x05>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x1c 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x1d 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x1e 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x1f 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ };*/
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004-AMA1-uart.dts b/configs/arm64/dts/phytium/ft2004-AMA1-uart.dts
new file mode 100644
index 00000000..0e073fec
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004-AMA1-uart.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 0x00 0x29980000 0x00 0x80000 0x00 0x29c00000 0x00 0x10000 0x00 0x29c10000 0x00 0x10000 0x00 0x29c20000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28000000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x06 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004-guest-eth.dts b/configs/arm64/dts/phytium/ft2004-guest-eth.dts
new file mode 100644
index 00000000..6a29d129
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004-guest-eth.dts
@@ -0,0 +1,131 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ clocks = <0x2 0x1>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ clocks = <0x2 0x1>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x3>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ interrupt-controller;
+ reg = <0x0 0x29900000 0x0 0x20000 0x0 0x29980000 0x0 0x80000 0x0 0x29c00000 0x0 0x10000 0x0 0x29c10000 0x0 0x10000 0x0 0x29c20000 0x0 0x10000>;
+ interrupts = <0x1 0x9 0x4>;
+ phandle = <0x1>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x6>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x3>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x4>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ dma-coherent;
+ ranges;
+
+ uart@28000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x28000000 0x0 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x2>;
+ reg-io-width = <0x4>;
+ interrupts = <0x0 0x6 0x4>;
+ clocks = <0x3 0x3>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ eth@2820c000 {
+ compatible = "snps,dwmac";
+ reg = <0x0 0x2820c000 0x0 0x2000>;
+ interrupts = <0x0 0x31 0x4>;
+ interrupt-names = "macirq";
+ clocks = <0x6>;
+ clock-names = "stmmaceth";
+ status = "ok";
+ snps,pbl = <0x10>;
+ snps,fixed-burst;
+ snps,axi-config = <0x7>;
+ snps,force_sf_dma_mode;
+ snps,multicast-filter-bins = <0x40>;
+ snps,perfect-filter-entries = <0x80>;
+ tx-fifo-depth = <0x1000>;
+ rx-fifo-depth = <0x1000>;
+ max-frame-size = <0x2328>;
+ phy-mode = "rgmii-rxid";
+ };
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004-main-eth.dts b/configs/arm64/dts/phytium/ft2004-main-eth.dts
new file mode 100644
index 00000000..a547a600
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004-main-eth.dts
@@ -0,0 +1,441 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ aliases {
+ ethernet0 = "/soc/eth@2820c000";
+ ethernet1 = "/soc/eth@28210000";
+ };
+
+ reserved-memory {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ reserved@b0000000 {
+ reg = <0x0 0xb0000000 0x0 0x40000000>;
+ no-map;
+ };
+ reserved@2300000000 {
+ reg = <0x23 0x00 0x0 0x10000000>;
+ no-map;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x3>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ interrupt-controller;
+ reg = <0x0 0x29900000 0x0 0x20000 0x0 0x29980000 0x0 0x80000 0x0 0x29c00000 0x0 0x10000 0x0 0x29c10000 0x0 0x10000 0x0 0x29c20000 0x0 0x10000>;
+ interrupts = <0x1 0x9 0x4>;
+ phandle = <0x1>;
+
+ gic-its@29920000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0x29920000 0x0 0x20000>;
+ phandle = <0x4>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x5>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x2>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x3>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ dma-coherent;
+ ranges;
+
+ gpio@28004000 {
+ compatible = "phytium,gpio";
+ reg = <0x0 0x28004000 0x0 0x1000>;
+ interrupts = <0x0 0xa 0x4>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ phandle = <0x7>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x0>;
+ nr-gpios = <0x8>;
+ };
+
+ portb {
+ compatible = "phytium,gpio-port";
+ reg = <0x1>;
+ nr-gpios = <0x8>;
+ };
+ };
+
+ gpio@28005000 {
+ compatible = "phytium,gpio";
+ reg = <0x0 0x28005000 0x0 0x1000>;
+ interrupts = <0x0 0xb 0x4>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x0>;
+ nr-gpios = <0x8>;
+ };
+
+ portb {
+ compatible = "phytium,gpio-port";
+ reg = <0x1>;
+ nr-gpios = <0x8>;
+ };
+ };
+
+ uart@28000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x28000000 0x0 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x2>;
+ reg-io-width = <0x4>;
+ interrupts = <0x0 0x6 0x4>;
+ clocks = <0x2 0x2>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart@28001000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x28001000 0x0 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x2>;
+ reg-io-width = <0x4>;
+ interrupts = <0x0 0x7 0x4>;
+ clocks = <0x2 0x2>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "ok";
+ };
+
+ uart@28002000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x28002000 0x0 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x2>;
+ reg-io-width = <0x4>;
+ interrupts = <0x0 0x8 0x4>;
+ clocks = <0x2 0x2>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart@28003000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x28003000 0x0 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x2>;
+ reg-io-width = <0x4>;
+ interrupts = <0x0 0x9 0x4>;
+ clocks = <0x2 0x2>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ sdci@28207c00 {
+ compatible = "phytium,sdci";
+ reg = <0x0 0x28207c00 0x0 0x100>;
+ interrupts = <0x0 0x14 0x4 0x0 0x15 0x4 0x0 0x16 0x4>;
+ clocks = <0x3 0x3>;
+ clock-names = "phytium_sdc_clk";
+ no-sdio;
+ no-mmc;
+ no-dma-coherent;
+ };
+
+ watchdog@2800a000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x2800b000 0x0 0x1000 0x0 0x2800a000 0x0 0x1000>;
+ interrupts = <0x0 0x10 0x4>;
+ timeout-sec = <0x1e>;
+ };
+
+ watchdog@28016000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x28017000 0x0 0x1000 0x0 0x28016000 0x0 0x1000>;
+ interrupts = <0x0 0x11 0x4>;
+ timeout-sec = <0x1e>;
+ };
+
+ rtc@2800d000 {
+ compatible = "phytium,rtc";
+ reg = <0x0 0x2800d000 0x0 0x1000>;
+ clocks = <0x2>;
+ clock-names = "rtc_pclk";
+ interrupts = <0x0 0x4 0x4>;
+ status = "disabled";
+ };
+
+ i2c@28006000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x28006000 0x0 0x1000>;
+ interrupts = <0x0 0xc 0x4>;
+ clocks = <0x2>;
+ status = "ok";
+ };
+
+ i2c@28007000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x28007000 0x0 0x1000>;
+ interrupts = <0x0 0xd 0x4>;
+ clocks = <0x2>;
+ status = "ok";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@28008000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x28008000 0x0 0x1000>;
+ interrupts = <0x0 0xe 0x4>;
+ clocks = <0x2>;
+ status = "disabled";
+ };
+
+ i2c@28009000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x28009000 0x0 0x1000>;
+ interrupts = <0x0 0xf 0x4>;
+ clocks = <0x2>;
+ status = "disabled";
+ };
+
+ spi@2800c000 {
+ compatible = "phytium,spi";
+ interrupts = <0x0 0x12 0x4>;
+ reg = <0x0 0x2800c000 0x0 0x1000>;
+ clocks = <0x2>;
+ num-cs = <0x4>;
+ status = "ok";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <0x7a1200>;
+ reg = <0x0>;
+ };
+ };
+
+ spi@28013000 {
+ compatible = "phytium,spi";
+ interrupts = <0x0 0x13 0x4>;
+ reg = <0x0 0x28013000 0x0 0x1000>;
+ clocks = <0x2>;
+ num-cs = <0x4>;
+ };
+
+ qspi@28014000 {
+ compatible = "phytium,qspi";
+ reg = <0x0 0x28014000 0x0 0x1000 0x0 0x0 0x0 0x2000000>;
+ reg-names = "qspi", "qspi_mm";
+ clocks = <0x3>;
+ status = "disabled";
+
+ flash@0 {
+ spi-rx-bus-width = <0x1>;
+ spi-max-frequency = <0x23c34600>;
+ };
+ };
+
+ pcie {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ reg = <0x0 0x40000000 0x0 0x10000000>;
+ msi-parent = <0x4>;
+ bus-range = <0x0 0xff>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x1c 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x1d 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x1e 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x1f 0x4>;
+ ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xf00000 0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000 0x3000000 0x10 0x0 0x10 0x0 0x10 0x0>;
+ };
+
+ stmmac-axi-config {
+ snps,wr_osr_lmt = <0x0>;
+ snps,rd_osr_lmt = <0x0>;
+ snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>;
+ phandle = <0x6>;
+ };
+
+ eth@28210000 {
+ compatible = "snps,dwmac";
+ reg = <0x0 0x28210000 0x0 0x2000>;
+ interrupts = <0x0 0x32 0x4>;
+ interrupt-names = "macirq";
+ clocks = <0x5>;
+ clock-names = "stmmaceth";
+ status = "ok";
+ snps,pbl = <0x10>;
+ snps,fixed-burst;
+ snps,axi-config = <0x6>;
+ snps,force_sf_dma_mode;
+ snps,multicast-filter-bins = <0x40>;
+ snps,perfect-filter-entries = <0x80>;
+ snps,rx-queues-to-use = <0x2>;
+ tx-fifo-depth = <0x1000>;
+ rx-fifo-depth = <0x1000>;
+ max-frame-size = <0x2328>;
+ phy-mode = "rgmii-id";
+ };
+
+ can@28207000 {
+ compatible = "phytium,can";
+ reg = <0x0 0x28207000 0x0 0x400>;
+ interrupts = <0x0 0x57 0x4>;
+ clocks = <0x3>;
+ clock-names = "phytium_can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ status = "ok";
+ };
+
+ can@28207400 {
+ compatible = "phytium,can";
+ reg = <0x0 0x28207400 0x0 0x400>;
+ interrupts = <0x0 0x5b 0x4>;
+ clocks = <0x3>;
+ clock-names = "phytium_can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ can@028207800 {
+ compatible = "phytium,can";
+ reg = <0x0 0x28207800 0x0 0x400>;
+ interrupts = <0x0 0x5c 0x4>;
+ clocks = <0x3>;
+ clock-names = "phytium_can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ hda@28206000 {
+ compatible = "phytium,hda";
+ reg = <0x0 0x28206000 0x0 0x1000>;
+ interrupts = <0x0 0x17 0x4>;
+ clocks = <0x2>;
+ clock-names = "phytium_hda_clk";
+ };
+ };
+
+ chosen {
+ stdout-path = "uart1:115200n8";
+ };
+
+ memory@00 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ memory@01 {
+ device_type = "memory";
+ reg = <0x20 0x0 0x3 0x80000000>;
+ };
+
+ firmware {
+
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
diff --git a/configs/arm64/dts/phytium/ft2004.dts b/configs/arm64/dts/phytium/ft2004.dts
new file mode 100644
index 00000000..8ed2be02
--- /dev/null
+++ b/configs/arm64/dts/phytium/ft2004.dts
@@ -0,0 +1,506 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ aliases {
+ ethernet0 = "/soc/eth@2820c000";
+ ethernet1 = "/soc/eth@28210000";
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ reserved@b0000000 {
+ reg = <0x00 0xb0000000 0x00 0x40000000>;
+ no-map;
+ };
+
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x00>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x00>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x01>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x00>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 0x00 0x29980000 0x00 0x80000 0x00 0x29c00000 0x00 0x10000 0x00 0x29c10000 0x00 0x10000 0x00 0x29c20000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+
+ gic-its@29920000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x00 0x29920000 0x00 0x20000>;
+ phandle = <0x05>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0x01 0x07 0x08>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ gpio@28004000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28004000 0x00 0x1000>;
+ interrupts = <0x00 0x0a 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ nr-gpios = <0x08>;
+ };
+
+ portb {
+ compatible = "phytium,gpio-port";
+ reg = <0x01>;
+ nr-gpios = <0x08>;
+ };
+ };
+
+ gpio@28005000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28005000 0x00 0x1000>;
+ interrupts = <0x00 0x0b 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ nr-gpios = <0x08>;
+ };
+
+ portb {
+ compatible = "phytium,gpio-port";
+ reg = <0x01>;
+ nr-gpios = <0x08>;
+ };
+ };
+
+ uart@28000000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x06 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+
+ uart@28001000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x07 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "ok";
+ };
+
+ uart@28002000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28002000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x08 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+
+ uart@28003000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28003000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x09 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+
+ sdci@28207c00 {
+ compatible = "phytium,sdci";
+ reg = <0x00 0x28207c00 0x00 0x100>;
+ interrupts = <0x00 0x14 0x04 0x00 0x15 0x04 0x00 0x16 0x04>;
+ clocks = <0x04 0x04>;
+ clock-names = "phytium_sdc_clk";
+ no-sdio;
+ no-mmc;
+ no-dma-coherent;
+ };
+
+ watchdog@2800a000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x00 0x2800b000 0x00 0x1000 0x00 0x2800a000 0x00 0x1000>;
+ interrupts = <0x00 0x10 0x04>;
+ timeout-sec = <0x1e>;
+ };
+
+ watchdog@28016000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x00 0x28017000 0x00 0x1000 0x00 0x28016000 0x00 0x1000>;
+ interrupts = <0x00 0x11 0x04>;
+ timeout-sec = <0x1e>;
+ };
+
+ i2c@28006000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x00 0x28006000 0x00 0x1000>;
+ interrupts = <0x00 0x0c 0x04>;
+ clocks = <0x03>;
+ status = "ok";
+ };
+
+ i2c@28007000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x00 0x28007000 0x00 0x1000>;
+ interrupts = <0x00 0x0d 0x04>;
+ clocks = <0x03>;
+ status = "ok";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@28008000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x00 0x28008000 0x00 0x1000>;
+ interrupts = <0x00 0x0e 0x04>;
+ clocks = <0x03>;
+ status = "disabled";
+ };
+
+ i2c@28009000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x00 0x28009000 0x00 0x1000>;
+ interrupts = <0x00 0x0f 0x04>;
+ clocks = <0x03>;
+ status = "disabled";
+ };
+
+ spi@2800c000 {
+ compatible = "phytium,spi";
+ interrupts = <0x00 0x12 0x04>;
+ reg = <0x00 0x2800c000 0x00 0x1000>;
+ clocks = <0x03>;
+ num-cs = <0x04>;
+ status = "ok";
+ };
+
+ spi@28013000 {
+ compatible = "phytium,spi";
+ interrupts = <0x00 0x13 0x04>;
+ reg = <0x00 0x28013000 0x00 0x1000>;
+ clocks = <0x03>;
+ num-cs = <0x04>;
+ };
+
+ qspi@28014000 {
+ compatible = "phytium,qspi";
+ reg = <0x00 0x28014000 0x00 0x1000 0x00 0x00 0x00 0x2000000>;
+ reg-names = "qspi\0qspi_mm";
+ clocks = <0x04>;
+ status = "ok";
+
+ flash@0 {
+ spi-rx-bus-width = <0x01>;
+ spi-max-frequency = <0x23c34600>;
+ };
+ };
+
+ pcie {
+ compatible = "pci-host-ecam-generic";
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x05>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x1c 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x1d 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x1e 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x1f 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ };
+
+ stmmac-axi-config {
+ snps,wr_osr_lmt = <0x00>;
+ snps,rd_osr_lmt = <0x00>;
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ phandle = <0x07>;
+ };
+
+ eth@2820c000 {
+ compatible = "snps,dwmac";
+ reg = <0x00 0x2820c000 0x00 0x2000>;
+ interrupts = <0x00 0x31 0x04>;
+ interrupt-names = "macirq";
+ clocks = <0x06>;
+ clock-names = "stmmaceth";
+ status = "ok";
+ snps,pbl = <0x10>;
+ snps,fixed-burst;
+ snps,axi-config = <0x07>;
+ snps,force_sf_dma_mode;
+ snps,multicast-filter-bins = <0x40>;
+ snps,perfect-filter-entries = <0x80>;
+ tx-fifo-depth = <0x1000>;
+ rx-fifo-depth = <0x1000>;
+ max-frame-size = <0x2328>;
+ phy-mode = "rgmii-rxid";
+ };
+
+ eth@28210000 {
+ compatible = "snps,dwmac";
+ reg = <0x00 0x28210000 0x00 0x2000>;
+ interrupts = <0x00 0x32 0x04>;
+ interrupt-names = "macirq";
+ clocks = <0x06>;
+ clock-names = "stmmaceth";
+ status = "ok";
+ snps,pbl = <0x10>;
+ snps,fixed-burst;
+ snps,axi-config = <0x07>;
+ snps,force_sf_dma_mode;
+ snps,multicast-filter-bins = <0x40>;
+ snps,perfect-filter-entries = <0x80>;
+ snps,rx-queues-to-use = <0x02>;
+ tx-fifo-depth = <0x1000>;
+ rx-fifo-depth = <0x1000>;
+ max-frame-size = <0x2328>;
+ phy-mode = "rgmii-rxid";
+ };
+
+ can@28207000 {
+ compatible = "phytium,can";
+ reg = <0x00 0x28207000 0x00 0x400>;
+ interrupts = <0x00 0x57 0x04>;
+ clocks = <0x04>;
+ clock-names = "phytium_can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ can@28207400 {
+ compatible = "phytium,can";
+ reg = <0x00 0x28207400 0x00 0x400>;
+ interrupts = <0x00 0x5b 0x04>;
+ clocks = <0x04>;
+ clock-names = "phytium_can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ can@028207800 {
+ compatible = "phytium,can";
+ reg = <0x00 0x28207800 0x00 0x400>;
+ interrupts = <0x00 0x5c 0x04>;
+ clocks = <0x04>;
+ clock-names = "phytium_can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ hda@28206000 {
+ compatible = "phytium,hda";
+ reg = <0x00 0x28206000 0x00 0x1000>;
+ interrupts = <0x00 0x17 0x04>;
+ clocks = <0x03>;
+ clock-names = "phytium_hda_clk";
+ };
+
+ mailbox@2a000000 {
+ compatible = "phytium,mbox";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ interrupts = <0x00 0x30 0x04>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03>;
+ clock-names = "apb_pclk";
+ phandle = <0x08>;
+ };
+
+ sram@2a006000 {
+ compatible = "phytium,ft2004-sram-ns\0mmio-sram";
+ reg = <0x00 0x2a006000 0x00 0x2000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x2a006000 0x2000>;
+
+ scpi-shmem@0 {
+ compatible = "phytium,ft2004-scpi-shmem";
+ reg = <0x1000 0x800>;
+ phandle = <0x09>;
+ };
+ };
+
+ scpi {
+ compatible = "arm,scpi";
+ mboxes = <0x08 0x00>;
+ shmem = <0x09>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <0x01>;
+ clock-indices = <0x00 0x01>;
+ clock-output-names = "c0\0c1";
+ phandle = <0x02>;
+ };
+ };
+
+ sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <0x01>;
+ };
+ };
+
+ lpc@0x20000000 {
+ compatible = "phytium,i8042";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <0x00 0x05 0x04>;
+ lpc_version = <0x01>;
+ status = "ok";
+ };
+ };
+
+ chosen {
+ stdout-path = "uart1:115200n8";
+ };
+
+ memory@00 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x00 0x80000000>;
+ };
+
+ memory@01 {
+ device_type = "memory";
+ reg = <0x20 0x00 0x03 0x80000000>;
+ };
+
+ firmware {
+
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
diff --git a/configs/arm64/dts/phytium/ftd2000-AMA0.dts b/configs/arm64/dts/phytium/ftd2000-AMA0.dts
new file mode 100644
index 00000000..e80385b7
--- /dev/null
+++ b/configs/arm64/dts/phytium/ftd2000-AMA0.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ interrupt-controller@29a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x29a00000 0x00 0x20000 0x00 0x29b00000 0x00 0x100000 0x00 0x29c00000 0x00 0x10000 0x00 0x29c10000 0x00 0x10000 0x00 0x29c20000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28000000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x06 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+ };
+};
diff --git a/configs/arm64/dts/phytium/ftd2000-AMA1.dts b/configs/arm64/dts/phytium/ftd2000-AMA1.dts
new file mode 100644
index 00000000..b30a448a
--- /dev/null
+++ b/configs/arm64/dts/phytium/ftd2000-AMA1.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "kvisor,domain";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ interrupt-controller@29a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x29a00000 0x00 0x20000 0x00 0x29b00000 0x00 0x100000 0x00 0x29c00000 0x00 0x10000 0x00 0x29c10000 0x00 0x10000 0x00 0x29c20000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28001000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x07 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+ };
+};
--
2.25.1
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