代码拉取完成，页面将自动刷新
From 563f4e3f53436146421c7ec78c8a6e541f45b698 Mon Sep 17 00:00:00 2001
From: huanglei <[email protected]>
Date: Mon, 26 Dec 2022 17:59:41 -0800
Subject: [PATCH 01/12] add phytium ftd2000 config files
---
.../arm64/phytium/d2000-inmate-board-rtos.c | 139 ++++++++
configs/arm64/phytium/d2000-main-board-rtos.c | 259 +++++++++++++++
configs/arm64/phytium/d2000-pc-inmate-rtos.c | 139 ++++++++
configs/arm64/phytium/d2000-pc-main-rtos.c | 259 +++++++++++++++
configs/arm64/phytium/ft2004-inmate-eth.c | 90 ++++++
configs/arm64/phytium/ft2004-inmate-ivshmem.c | 149 +++++++++
configs/arm64/phytium/ft2004-inmate.c | 149 +++++++++
configs/arm64/phytium/ft2004-main-eth.c | 291 +++++++++++++++++
configs/arm64/phytium/ft2004-main-ivshmem.c | 306 ++++++++++++++++++
configs/arm64/phytium/ft2004-main.c | 306 ++++++++++++++++++
10 files changed, 2087 insertions(+)
create mode 100644 configs/arm64/phytium/d2000-inmate-board-rtos.c
create mode 100644 configs/arm64/phytium/d2000-main-board-rtos.c
create mode 100644 configs/arm64/phytium/d2000-pc-inmate-rtos.c
create mode 100644 configs/arm64/phytium/d2000-pc-main-rtos.c
create mode 100644 configs/arm64/phytium/ft2004-inmate-eth.c
create mode 100644 configs/arm64/phytium/ft2004-inmate-ivshmem.c
create mode 100644 configs/arm64/phytium/ft2004-inmate.c
create mode 100644 configs/arm64/phytium/ft2004-main-eth.c
create mode 100644 configs/arm64/phytium/ft2004-main-ivshmem.c
create mode 100644 configs/arm64/phytium/ft2004-main.c
diff --git a/configs/arm64/phytium/d2000-inmate-board-rtos.c b/configs/arm64/phytium/d2000-inmate-board-rtos.c
new file mode 100644
index 00000000..1a56a99c
--- /dev/null
+++ b/configs/arm64/phytium/d2000-inmate-board-rtos.c
@@ -0,0 +1,139 @@
+/*
+ * jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[10];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "linux",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+ .cpu_reset_address = 0x80100000,
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 101,
+
+ .console = {
+ .address = 0x28001000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0x1,
+ },
+
+ .irqchips = {
+ {
+ .address = 0x29A00000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 1 << (38 - 32),
+ 0,
+ 0,
+ 1 << (101 + 32 - 128),
+ },
+ },
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0x2105000000,
+ .virt_start = 0x2105000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x2105001000,
+ .virt_start = 0x2105001000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x210500a000,
+ .virt_start = 0x210500a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x210500c000,
+ .virt_start = 0x210500c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x210500e000,
+ .virt_start = 0x210500e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* UART */{
+ .phys_start = 0x28001000,
+ .virt_start = 0x28001000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* freertos bin */ {
+ .phys_start = 0x2106000000,
+ .virt_start = 0x80000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+
+ /* inmate bin */ {
+ .phys_start = 0x2116000000,
+ .virt_start = 0,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+
+ /* RAM & linux kernel initrd */ {
+ .phys_start = 0x2117000000,
+ .virt_start = 0x2117000000,
+ .size = 0xc000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x90000000,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 1,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
diff --git a/configs/arm64/phytium/d2000-main-board-rtos.c b/configs/arm64/phytium/d2000-main-board-rtos.c
new file mode 100644
index 00000000..c70b29f6
--- /dev/null
+++ b/configs/arm64/phytium/d2000-main-board-rtos.c
@@ -0,0 +1,259 @@
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[4];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[11];
+ struct jailhouse_pci_capability pci_caps[81];
+} __attribute__((packed)) config = {
+.header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0x2104000000,
+ .size = 0x1000000,
+ },
+ .debug_console = {
+ .address = 0x28000000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO|JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x0000000040000000,
+ .pci_mmconfig_end_bus = 0xFF,
+ .pci_is_virtual = 1,
+ .pci_domain = 1,
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x0000000029A00000,
+ .gicr_base = 0x0000000029B00000,
+ .gicc_base = 0x0000000029C00000,
+ .gich_base = 0x0000000029C10000,
+ .gicv_base = 0x0000000029C20000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "Rootcell",
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .num_pci_caps = ARRAY_SIZE(config.pci_caps),
+ .vpci_irq_base = 100,
+ },
+},
+.cpus = { 0xf, },
+.mem_regions = {
+ {.phys_start=0x28000000, .virt_start=0x28000000, .size=0x58000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},
+ {.phys_start=0x80000000, .virt_start=0x80000000, .size=0x7c000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE},
+ {.phys_start=0x1000000000, .virt_start=0x1000000000, .size=0x1000000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},
+ {.phys_start=0x2000000000, .virt_start=0x2000000000, .size=0x180000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE},
+},
+.irqchips = {
+ {
+ .address = 0x0000000029A00000,
+ .pin_base = 32,
+ .pin_bitmap = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
+ },
+},
+.pci_devices = {
+
+ /* PCIDevice: 0000:00:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x0, .caps_start = 0, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010000000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:01.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x8, .caps_start = 8, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010100000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:02.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x10, .caps_start = 16, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010200000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:03.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x18, .caps_start = 24, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010300000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:04.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x20, .caps_start = 32, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010400000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:05.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x28, .caps_start = 40, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010500000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:02:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x200, .caps_start = 48, .num_caps = 8,
+ .num_msi_vectors = 1, .msi_64bits = 1, .msi_maskable = 0,
+ .num_msix_vectors = 0, .msix_region_size = 0x0, .msix_address = 0x0,
+ .bar_mask={0xf0000000, 0xffffffff, 0xfffc0000, 0xffffffff, 0xffffff00, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:02:00.1 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x201, .caps_start = 56, .num_caps = 6,
+ .num_msi_vectors = 1, .msi_64bits = 1, .msi_maskable = 0,
+ .num_msix_vectors = 0, .msix_region_size = 0x0, .msix_address = 0x0,
+ .bar_mask={0xffffc000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:03:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x300, .caps_start = 62, .num_caps = 5,
+ .num_msi_vectors = 1, .msi_64bits = 0, .msi_maskable = 0,
+ .num_msix_vectors = 0, .msix_region_size = 0x0, .msix_address = 0x0,
+ .bar_mask={0xfffffff8, 0xfffffffc, 0xfffffff8, 0xfffffffc, 0xffffffe0, 0xfffff800, },
+ },
+
+ /* PCIDevice: 0000:04:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x400, .caps_start = 67, .num_caps = 8,
+ .num_msi_vectors = 8, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 16, .msix_region_size = 0x1000, .msix_address = 0x58202000,
+ .bar_mask={0xffffc000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:06:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x600, .caps_start = 75, .num_caps = 6,
+ .num_msi_vectors = 8, .msi_64bits = 1, .msi_maskable = 0,
+ .num_msix_vectors = 8, .msix_region_size = 0x1000, .msix_address = 0x58301000,
+ .bar_mask={0xffffe000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+},
+.pci_caps = {
+
+ /* PCIDevice: 0000:00:00.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:01.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:02.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:03.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:04.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:05.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:02:00.0 */
+ {.id=PCI_CAP_ID_VNDR, .start=0x48, .len=2, .flags=0},
+ {.id=PCI_CAP_ID_PM, .start=0x50, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x58, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xa0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x150, .len=64, .flags=0},
+ {.id=PCI_EXT_CAP_ID_REBAR, .start=0x200, .len=2, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x270, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:02:00.1 */
+ {.id=PCI_CAP_ID_VNDR, .start=0x48, .len=2, .flags=0},
+ {.id=PCI_CAP_ID_PM, .start=0x50, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x58, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xa0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x150, .len=64, .flags=0},
+
+ /* PCIDevice: 0000:03:00.0 */
+ {.id=PCI_CAP_ID_PM, .start=0x40, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0x50, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x70, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_SATA, .start=0xe0, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x100, .len=64, .flags=0},
+
+ /* PCIDevice: 0000:04:00.0 */
+ {.id=PCI_CAP_ID_PM, .start=0x40, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0x50, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x70, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xb0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x100, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x158, .len=16, .flags=0},
+ {.id=PCI_EXT_CAP_ID_LTR, .start=0x178, .len=8, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x180, .len=2, .flags=0},
+
+ /* PCIDevice: 0000:06:00.0 */
+ {.id=PCI_CAP_ID_PM, .start=0x50, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0x70, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0x90, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0xa0, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x100, .len=64, .flags=0},
+ {.id=PCI_EXT_CAP_ID_LTR, .start=0x150, .len=8, .flags=0},
+},
+};
diff --git a/configs/arm64/phytium/d2000-pc-inmate-rtos.c b/configs/arm64/phytium/d2000-pc-inmate-rtos.c
new file mode 100644
index 00000000..3e9f6de1
--- /dev/null
+++ b/configs/arm64/phytium/d2000-pc-inmate-rtos.c
@@ -0,0 +1,139 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[10];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "linux",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+ .cpu_reset_address = 0x80100000,
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 101,
+
+ .console = {
+ .address = 0x28001000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0x1,
+ },
+
+ .irqchips = {
+ {
+ .address = 0x29A00000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 1 << (38 - 32),
+ 0,
+ 0,
+ 1 << (101 + 32 - 128),
+ },
+ },
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0x2105000000,
+ .virt_start = 0x2105000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x2105001000,
+ .virt_start = 0x2105001000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x210500a000,
+ .virt_start = 0x210500a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x210500c000,
+ .virt_start = 0x210500c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0x210500e000,
+ .virt_start = 0x210500e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* UART */{
+ .phys_start = 0x28001000,
+ .virt_start = 0x28001000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* freertos bin */ {
+ .phys_start = 0x2106000000,
+ .virt_start = 0x80000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+
+ /* inmate bin */ {
+ .phys_start = 0x2116000000,
+ .virt_start = 0,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+
+ /* RAM & linux kernel initrd */ {
+ .phys_start = 0x2117000000,
+ .virt_start = 0x2117000000,
+ .size = 0xc000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x90000000,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 1,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
diff --git a/configs/arm64/phytium/d2000-pc-main-rtos.c b/configs/arm64/phytium/d2000-pc-main-rtos.c
new file mode 100644
index 00000000..5982613d
--- /dev/null
+++ b/configs/arm64/phytium/d2000-pc-main-rtos.c
@@ -0,0 +1,259 @@
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[4];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[11];
+ struct jailhouse_pci_capability pci_caps[81];
+} __attribute__((packed)) config = {
+.header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0x2104000000,
+ .size = 0x1000000,
+ },
+ .debug_console = {
+ .address = 0x28001000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO|JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x0000000040000000,
+ .pci_mmconfig_end_bus = 0xFF,
+ .pci_is_virtual = 1,
+ .pci_domain = 1,
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x0000000029A00000,
+ .gicr_base = 0x0000000029B00000,
+ .gicc_base = 0x0000000029C00000,
+ .gich_base = 0x0000000029C10000,
+ .gicv_base = 0x0000000029C20000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "RootCell",
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .num_pci_caps = ARRAY_SIZE(config.pci_caps),
+ .vpci_irq_base = 100,
+ },
+},
+.cpus = { 0xff, },
+.mem_regions = {
+ {.phys_start=0x28000000, .virt_start=0x28000000, .size=0x58000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},
+ {.phys_start=0x80000000, .virt_start=0x80000000, .size=0x7c000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE},
+ {.phys_start=0x1000000000, .virt_start=0x1000000000, .size=0x1000000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO},
+ {.phys_start=0x2000000000, .virt_start=0x2000000000, .size=0x180000000, .flags=JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE},
+},
+.irqchips = {
+ {
+ .address = 0x0000000029A00000,
+ .pin_base = 32,
+ .pin_bitmap = {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
+ },
+},
+.pci_devices = {
+
+ /* PCIDevice: 0000:00:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x0, .caps_start = 0, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010000000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:01.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x8, .caps_start = 8, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010100000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:02.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x10, .caps_start = 16, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010200000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:03.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x18, .caps_start = 24, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010300000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:04.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x20, .caps_start = 32, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010400000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:00:05.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE, .domain = 0x0, .bdf = 0x28, .caps_start = 40, .num_caps = 8,
+ .num_msi_vectors = 32, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 1, .msix_region_size = 0x1000, .msix_address = 0x1010500000,
+ .bar_mask={0xfff00000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:02:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x200, .caps_start = 48, .num_caps = 8,
+ .num_msi_vectors = 1, .msi_64bits = 1, .msi_maskable = 0,
+ .num_msix_vectors = 0, .msix_region_size = 0x0, .msix_address = 0x0,
+ .bar_mask={0xf0000000, 0xffffffff, 0xfffc0000, 0xffffffff, 0xffffff00, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:02:00.1 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x201, .caps_start = 56, .num_caps = 6,
+ .num_msi_vectors = 1, .msi_64bits = 1, .msi_maskable = 0,
+ .num_msix_vectors = 0, .msix_region_size = 0x0, .msix_address = 0x0,
+ .bar_mask={0xffffc000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:03:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x300, .caps_start = 62, .num_caps = 5,
+ .num_msi_vectors = 1, .msi_64bits = 0, .msi_maskable = 0,
+ .num_msix_vectors = 0, .msix_region_size = 0x0, .msix_address = 0x0,
+ .bar_mask={0xfffffff8, 0xfffffffc, 0xfffffff8, 0xfffffffc, 0xffffffe0, 0xfffff800, },
+ },
+
+ /* PCIDevice: 0000:04:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x400, .caps_start = 67, .num_caps = 8,
+ .num_msi_vectors = 8, .msi_64bits = 1, .msi_maskable = 1,
+ .num_msix_vectors = 16, .msix_region_size = 0x1000, .msix_address = 0x58202000,
+ .bar_mask={0xffffc000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+
+ /* PCIDevice: 0000:06:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE, .domain = 0x0, .bdf = 0x600, .caps_start = 75, .num_caps = 6,
+ .num_msi_vectors = 8, .msi_64bits = 1, .msi_maskable = 0,
+ .num_msix_vectors = 8, .msix_region_size = 0x1000, .msix_address = 0x58301000,
+ .bar_mask={0xffffe000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
+ },
+},
+.pci_caps = {
+
+ /* PCIDevice: 0000:00:00.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:01.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:02.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:03.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:04.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:00:05.0 */
+ {.id=PCI_CAP_ID_EXP, .start=0x80, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xd0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xe0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_PM, .start=0xf8, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x110, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x200, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x300, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:02:00.0 */
+ {.id=PCI_CAP_ID_VNDR, .start=0x48, .len=2, .flags=0},
+ {.id=PCI_CAP_ID_PM, .start=0x50, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x58, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xa0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x150, .len=64, .flags=0},
+ {.id=PCI_EXT_CAP_ID_REBAR, .start=0x200, .len=2, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x270, .len=16, .flags=0},
+
+ /* PCIDevice: 0000:02:00.1 */
+ {.id=PCI_CAP_ID_VNDR, .start=0x48, .len=2, .flags=0},
+ {.id=PCI_CAP_ID_PM, .start=0x50, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x58, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0xa0, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_VNDR, .start=0x100, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x150, .len=64, .flags=0},
+
+ /* PCIDevice: 0000:03:00.0 */
+ {.id=PCI_CAP_ID_PM, .start=0x40, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0x50, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x70, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_SATA, .start=0xe0, .len=2, .flags=0},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x100, .len=64, .flags=0},
+
+ /* PCIDevice: 0000:04:00.0 */
+ {.id=PCI_CAP_ID_PM, .start=0x40, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0x50, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0x70, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0xb0, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x100, .len=64, .flags=0},
+ {.id=PCI_CAP_ID_EXP, .start=0x158, .len=16, .flags=0},
+ {.id=PCI_EXT_CAP_ID_LTR, .start=0x178, .len=8, .flags=0},
+ {.id=PCI_EXT_CAP_ID_L1SS, .start=0x180, .len=2, .flags=0},
+
+ /* PCIDevice: 0000:06:00.0 */
+ {.id=PCI_CAP_ID_PM, .start=0x50, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0x70, .len=10, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0x90, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0xa0, .len=20, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x100, .len=64, .flags=0},
+ {.id=PCI_EXT_CAP_ID_LTR, .start=0x150, .len=8, .flags=0},
+},
+};
diff --git a/configs/arm64/phytium/ft2004-inmate-eth.c b/configs/arm64/phytium/ft2004-inmate-eth.c
new file mode 100644
index 00000000..31a6123b
--- /dev/null
+++ b/configs/arm64/phytium/ft2004-inmate-eth.c
@@ -0,0 +1,90 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[5];
+ struct jailhouse_irqchip irqchips[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "ft2004-inmate-eth",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | JAILHOUSE_CELL_AARCH32,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .cpu_reset_address = 0x80100000,
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+
+ .console = {
+ .address = 0x28001000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0x1,
+ },
+
+ .irqchips = {
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ (1 << (39 -32)) | (1 << (42 -32)),
+ 1 << (81 - 64),
+ 0,
+ 0,
+ },
+ },
+ },
+
+ .mem_regions = {
+ /* UART */{
+ .phys_start = 0x28001000,
+ .virt_start = 0x28001000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* ETH0 */ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* GPIO */{
+ .phys_start = 0x28004000,
+ .virt_start = 0x28004000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xc0000000,
+ .virt_start = 0xc0000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x90000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+};
+
diff --git a/configs/arm64/phytium/ft2004-inmate-ivshmem.c b/configs/arm64/phytium/ft2004-inmate-ivshmem.c
new file mode 100644
index 00000000..3b340cdf
--- /dev/null
+++ b/configs/arm64/phytium/ft2004-inmate-ivshmem.c
@@ -0,0 +1,149 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[11];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "ft2004-inmate-ivshmem",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | JAILHOUSE_CELL_AARCH32,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .cpu_reset_address = 0x80100000,
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 101,
+
+ .console = {
+ .address = 0x28001000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0x1,
+ },
+
+ .irqchips = {
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ (1 << (38-32)) | (1 << (44-32)) | (1 << (50-32)),
+ 0,
+ 1 << (119-96),
+ 1 << (101 + 32 - 128),
+ },
+ },
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0xb1000000,
+ .virt_start = 0xb1000000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb1010000,
+ .virt_start = 0xb1010000,
+ .size = 0x90000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb10a0000,
+ .virt_start = 0xb10a0000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb10c0000,
+ .virt_start = 0xb10c0000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb10e0000,
+ .virt_start = 0xb10e0000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* UART */{
+ .phys_start = 0x28001000,
+ .virt_start = 0x28001000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* IOMUX */
+ {
+ .phys_start = 0x28180000,
+ .virt_start = 0x28180000,
+ .size = 0x0500,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO_32,
+ },
+ /* CAN 0-2 */
+ {
+ .phys_start = 0x28207000,
+ .virt_start = 0x28207000,
+ .size = 0xc00,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO_32,
+ },
+ /* ETH1 */ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xb2000000,
+ .virt_start = 0x80000000,
+ .size = 0x0f000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x9000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 1,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
+
diff --git a/configs/arm64/phytium/ft2004-inmate.c b/configs/arm64/phytium/ft2004-inmate.c
new file mode 100644
index 00000000..243c90cb
--- /dev/null
+++ b/configs/arm64/phytium/ft2004-inmate.c
@@ -0,0 +1,149 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[11];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "ft2004-inmate",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | JAILHOUSE_CELL_AARCH32,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .cpu_reset_address = 0x80100000,
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 101,
+
+ .console = {
+ .address = 0x28000000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0x1,
+ },
+
+ .irqchips = {
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ (1 << (38-32)) | (1 << (44-32)) | (1 << (50-32)),
+ 0,
+ 1 << (119-96),
+ 1 << (101 + 32 - 128),
+ },
+ },
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0xb1000000,
+ .virt_start = 0xb1000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb1001000,
+ .virt_start = 0xb1001000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb100a000,
+ .virt_start = 0xb100a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb100c000,
+ .virt_start = 0xb100c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb100e000,
+ .virt_start = 0xb100e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* UART */{
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* IOMUX */
+ {
+ .phys_start = 0x28180000,
+ .virt_start = 0x28180000,
+ .size = 0x0500,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO_32,
+ },
+ /* CAN 0-2 */
+ {
+ .phys_start = 0x28207000,
+ .virt_start = 0x28207000,
+ .size = 0xc00,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO_32,
+ },
+ /* ETH1 */ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xb2000000,
+ .virt_start = 0x80000000,
+ .size = 0x0f000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x9000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 1,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
+
diff --git a/configs/arm64/phytium/ft2004-main-eth.c b/configs/arm64/phytium/ft2004-main-eth.c
new file mode 100644
index 00000000..c68731e3
--- /dev/null
+++ b/configs/arm64/phytium/ft2004-main-eth.c
@@ -0,0 +1,291 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[26];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xb0000000,
+ .size = 0x01000000,
+ },
+ .debug_console = {
+ .address = 0x28000000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x30000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = 1,
+
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x29900000,
+ .gicr_base = 0x29980000,
+ .gicc_base = 0x29c00000,
+ .gich_base = 0x29c10000,
+ .gicv_base = 0x29c20000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "ft2004-main-eth",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 100,
+ },
+ },
+
+ .cpus = {
+ 0xf,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0xb1000000,
+ .virt_start = 0xb1000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb1001000,
+ .virt_start = 0xb1001000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb100a000,
+ .virt_start = 0xb100a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb100c000,
+ .virt_start = 0xb100c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb100e000,
+ .virt_start = 0xb100e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x80000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x2000000000,
+ .virt_start = 0x2000000000,
+ .size = 0x380000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UART 0-3 */
+ {
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x4000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GPIO 0-1 */
+ {
+ .phys_start = 0x28004000,
+ .virt_start = 0x28004000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* I2C 0-1 */
+ {
+ .phys_start = 0x28006000,
+ .virt_start = 0x28006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 0 */
+ {
+ .phys_start = 0x2800a000,
+ .virt_start = 0x2800a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 1 */
+ {
+ .phys_start = 0x28016000,
+ .virt_start = 0x28016000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 0 */
+ {
+ .phys_start = 0x2800c000,
+ .virt_start = 0x2800c000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 1 */
+ {
+ .phys_start = 0x28013000,
+ .virt_start = 0x28013000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* QSPI */
+ {
+ .phys_start = 0x28014000,
+ .virt_start = 0x28014000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* HDA */
+ {
+ .phys_start = 0x28206000,
+ .virt_start = 0x28206000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* CAN 0-2 and SDCI*/
+ {
+ .phys_start = 0x28207000,
+ .virt_start = 0x28207000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH0 */
+ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH1 */
+ {
+ .phys_start = 0x28210000,
+ .virt_start = 0x28210000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Mailbox */
+ {
+ .phys_start = 0x2a000000,
+ .virt_start = 0x2a000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SRAM */
+ {
+ .phys_start = 0x2a006000,
+ .virt_start = 0x2a006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GIC ITS */
+ {
+ .phys_start = 0x29920000,
+ .virt_start = 0x29920000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe ECAM */
+ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe IO */
+ {
+ .phys_start = 0x50000000,
+ .virt_start = 0x50000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem32 */
+ {
+ .phys_start = 0x58000000,
+ .virt_start = 0x58000000,
+ .size = 0x28000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem64 */
+ {
+ .phys_start = 0x1000000000,
+ .virt_start = 0x1000000000,
+ .size = 0x1000000000,
+ //.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ // JAILHOUSE_MEM_IO,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 0,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
diff --git a/configs/arm64/phytium/ft2004-main-ivshmem.c b/configs/arm64/phytium/ft2004-main-ivshmem.c
new file mode 100644
index 00000000..db8ac68e
--- /dev/null
+++ b/configs/arm64/phytium/ft2004-main-ivshmem.c
@@ -0,0 +1,306 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[28];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xb0000000,
+ .size = 0x01000000,
+ },
+ .debug_console = {
+ .address = 0x28001000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x30000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = 1,
+
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x29900000,
+ .gicr_base = 0x29980000,
+ .gicc_base = 0x29c00000,
+ .gich_base = 0x29c10000,
+ .gicv_base = 0x29c20000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "ft2004-main-ivshmem",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 100,
+ },
+ },
+
+ .cpus = {
+ 0xf,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0xb1000000,
+ .virt_start = 0xb1000000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb1010000,
+ .virt_start = 0xb1010000,
+ .size = 0x90000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb10a0000,
+ .virt_start = 0xb10a0000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb10c0000,
+ .virt_start = 0xb10c0000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb10e0000,
+ .virt_start = 0xb10e0000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x80000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x2000000000,
+ .virt_start = 0x2000000000,
+ .size = 0x380000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UART 0-3 */
+ {
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x4000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GPIO 0-1 */
+ {
+ .phys_start = 0x28004000,
+ .virt_start = 0x28004000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* IOMUX */
+ {
+ .phys_start = 0x28180000,
+ .virt_start = 0x28180000,
+ .size = 0x0500,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO_32,
+ },
+ /* I2C 0-1 */
+ {
+ .phys_start = 0x28006000,
+ .virt_start = 0x28006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 0 */
+ {
+ .phys_start = 0x2800a000,
+ .virt_start = 0x2800a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 1 */
+ {
+ .phys_start = 0x28016000,
+ .virt_start = 0x28016000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 0 */
+ {
+ .phys_start = 0x2800c000,
+ .virt_start = 0x2800c000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 1 */
+ {
+ .phys_start = 0x28013000,
+ .virt_start = 0x28013000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* QSPI */
+ {
+ .phys_start = 0x28014000,
+ .virt_start = 0x28014000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* HDA */
+ {
+ .phys_start = 0x28206000,
+ .virt_start = 0x28206000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* CAN 0-2 */
+ {
+ .phys_start = 0x28207000,
+ .virt_start = 0x28207000,
+ .size = 0xc00,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SDCI */
+ {
+ .phys_start = 0x28207c00,
+ .virt_start = 0x28207c00,
+ .size = 0x400,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH0 */
+ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH1 */
+ {
+ .phys_start = 0x28210000,
+ .virt_start = 0x28210000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Mailbox */
+ {
+ .phys_start = 0x2a000000,
+ .virt_start = 0x2a000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SRAM */
+ {
+ .phys_start = 0x2a006000,
+ .virt_start = 0x2a006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GIC ITS */
+ {
+ .phys_start = 0x29920000,
+ .virt_start = 0x29920000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe ECAM */
+ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe IO */
+ {
+ .phys_start = 0x50000000,
+ .virt_start = 0x50000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem32 */
+ {
+ .phys_start = 0x58000000,
+ .virt_start = 0x58000000,
+ .size = 0x28000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem64 */
+ {
+ .phys_start = 0x1000000000,
+ .virt_start = 0x1000000000,
+ .size = 0x1000000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 0,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
diff --git a/configs/arm64/phytium/ft2004-main.c b/configs/arm64/phytium/ft2004-main.c
new file mode 100644
index 00000000..a8fb094c
--- /dev/null
+++ b/configs/arm64/phytium/ft2004-main.c
@@ -0,0 +1,306 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[28];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xb0000000,
+ .size = 0x01000000,
+ },
+ .debug_console = {
+ .address = 0x28001000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x30000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = 1,
+
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x29900000,
+ .gicr_base = 0x29980000,
+ .gicc_base = 0x29c00000,
+ .gich_base = 0x29c10000,
+ .gicv_base = 0x29c20000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "ft2004-main",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 100,
+ },
+ },
+
+ .cpus = {
+ 0xf,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0xb1000000,
+ .virt_start = 0xb1000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb1001000,
+ .virt_start = 0xb1001000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb100a000,
+ .virt_start = 0xb100a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb100c000,
+ .virt_start = 0xb100c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb100e000,
+ .virt_start = 0xb100e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x80000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x2000000000,
+ .virt_start = 0x2000000000,
+ .size = 0x380000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UART 0-3 */
+ {
+ .phys_start = 0x28001000,
+ .virt_start = 0x28001000,
+ .size = 0x4000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GPIO 0-1 */
+ {
+ .phys_start = 0x28004000,
+ .virt_start = 0x28004000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* IOMUX */
+ {
+ .phys_start = 0x28180000,
+ .virt_start = 0x28180000,
+ .size = 0x0500,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO_32,
+ },
+ /* I2C 0-1 */
+ {
+ .phys_start = 0x28006000,
+ .virt_start = 0x28006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 0 */
+ {
+ .phys_start = 0x2800a000,
+ .virt_start = 0x2800a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 1 */
+ {
+ .phys_start = 0x28016000,
+ .virt_start = 0x28016000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 0 */
+ {
+ .phys_start = 0x2800c000,
+ .virt_start = 0x2800c000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 1 */
+ {
+ .phys_start = 0x28013000,
+ .virt_start = 0x28013000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* QSPI */
+ {
+ .phys_start = 0x28014000,
+ .virt_start = 0x28014000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* HDA */
+ {
+ .phys_start = 0x28206000,
+ .virt_start = 0x28206000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* CAN 0-2 */
+ {
+ .phys_start = 0x28207000,
+ .virt_start = 0x28207000,
+ .size = 0xc00,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SDCI */
+ {
+ .phys_start = 0x28207c00,
+ .virt_start = 0x28207c00,
+ .size = 0x400,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH0 */
+ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH1 */
+ {
+ .phys_start = 0x28210000,
+ .virt_start = 0x28210000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Mailbox */
+ {
+ .phys_start = 0x2a000000,
+ .virt_start = 0x2a000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SRAM */
+ {
+ .phys_start = 0x2a006000,
+ .virt_start = 0x2a006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GIC ITS */
+ {
+ .phys_start = 0x29920000,
+ .virt_start = 0x29920000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe ECAM */
+ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe IO */
+ {
+ .phys_start = 0x50000000,
+ .virt_start = 0x50000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem32 */
+ {
+ .phys_start = 0x58000000,
+ .virt_start = 0x58000000,
+ .size = 0x28000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem64 */
+ {
+ .phys_start = 0x1000000000,
+ .virt_start = 0x1000000000,
+ .size = 0x1000000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 0,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
--
2.25.1
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