// configuration
	
                // value set here used when building using Vivado UI
                DEFc    RX_CFG          4
                //DEFc    RX_CFG          8
                //DEFc    RX_CFG          3
                //DEFc    RX_CFG          14
                //DEFc    RX_CFG          0

            #if RX_CFG
				DEFh	USE_SDR	        1
			#else
				DEFh	USE_SDR	        0
			#endif
				DEFh	USE_GPS	        1
				
				
				// options

				DEFh    ARTIX_7A35      1
				DEFh    ZYNQ_7007       0
				
				DEFp	FPGA_VER		4'd1
				DEFp	FW_ID			0x5000

				DEFp	ADC_BITS		14
				DEFp	DEFAULT_NSYNC	2			// bits in synchronizers
				
				DEFh	USE_MIX_DDS		1
				DEFh	USE_GEN			0
				DEFh	USE_HBEAT		0
				DEFh	USE_LOGGER		1
				DEFh	USE_CPU_CTR		1
				DEFh	USE_DEBUG		1
                DEFh	USE_RX_SEQ		0		// due to out-of-brams w/ rx4 config
				
				DEFh	USE_VIVADO		1
				DEFh	SERIES_7        1
				DEFh	SPI_PUMP_CHECK	0
				DEFh	STACK_CHECK		0
				DEFh	SND_SEQ_CHECK	0
				DEFh    SND_TIMING_CK   0
				DEFh    MEAS_CIC_OUT    0
				
				DEFp    FPGA_ID_RX4_WF4     4'd0
				DEFp    FPGA_ID_RX8_WF2     4'd1
				DEFp    FPGA_ID_RX3_WF3     4'd2
				DEFp    FPGA_ID_RX14_WF0    4'd3
				DEFp    FPGA_ID_GPS         4'd3

				DEFp    NUM_CMDS_BASE   13
				DEFp	NUM_CMDS_GPS    16

			#if USE_SDR
				DEFp    NUM_CMDS_SDR    12
				DEFh    CFG_GPS_ONLY    0
			#else
				DEFp    NUM_CMDS_SDR    0
				DEFh    CFG_GPS_ONLY    1
			#endif

				DEFp	NUM_CMDS		NUM_CMDS_BASE + NUM_CMDS_SDR + NUM_CMDS_GPS


; ============================================================================

				// SPI
				DEFh	SPI_32			1
				DEFp    SPIBUF_W        2048        // limited by use of single 2K x 16 (36 kb) BRAM in host.v
				DEFp    SPIBUF_B        SPIBUF_W * 2
				DEFp    SPIBUF_BMAX     SPIBUF_W - 1 * 2    // can't use last word for some reason

				// rx
				DEFp	RX1_20K_DECIM   823			// to get near integer multiple for WSPR sample rate
				DEFp	RX2_20K_DECIM   4			// 823*4 = 3292, 66.6666M/3292 = 20251.094 Hz

				DEFp	RX1_12K_DECIM   505			// to get near integer multiple for WSPR sample rate
				DEFp	RX2_12K_DECIM   11			// 505*11 = 5555, 66.6666M/5555 = 12001.188 Hz

                DEFp    MAX_SND_RATE    20250
                DEFp    SND_RATE_3CH    20250
                DEFp    SND_RATE_4CH    12000
                DEFp    SND_RATE_8CH    12000
                DEFp    SND_RATE_14CH   12000

                DEFp    RX_DECIM_3CH    RX1_20K_DECIM * RX2_20K_DECIM
                DEFp    RX_DECIM_4CH    RX1_12K_DECIM * RX2_12K_DECIM
                DEFp    RX_DECIM_8CH    RX1_12K_DECIM * RX2_12K_DECIM
                DEFp    RX_DECIM_14CH   RX1_12K_DECIM * RX2_12K_DECIM

                DEFp    RXBUF_SIZE_3CH  16384       // given 16k x 16b audio buffer in receiver.v
                DEFp    RXBUF_SIZE_4CH   8192       // given  8k x 16b audio buffer in receiver.v
                DEFp    RXBUF_SIZE_8CH  16384       // given 16k x 16b audio buffer in receiver.v
                DEFp    RXBUF_SIZE_14CH 32768       // given 32k x 16b audio buffer in receiver.v
                
                DEFp    SND_INTR_3CH    11200
                DEFp    SND_INTR_4CH    14000
                DEFp    SND_INTR_8CH     7000
                DEFp    SND_INTR_14CH    4000

                // for SPIBUF_W = 2048, RX_CHANS = 3, => nrx_samps = 226
			    // 1/(20250/nrx_samps) = interrupt every 11.2 ms / 90 Hz
                // for RXBUF_SIZE_3CH = 16384 => nrx_bufs = 8

                // for SPIBUF_W = 2048, RX_CHANS = 4, => nrx_samps = 170
			    // 1/(12000/nrx_samps) = interrupt every 14 ms / 71 Hz
                // for RXBUF_SIZE_3CH = 8192 => nrx_bufs = 4

                // for SPIBUF_W = 2048, RX_CHANS = 8, => nrx_samps = 85
			    // 1/(12000/nrx_samps) = interrupt every 7 ms / 141 Hz
                // for RXBUF_SIZE_8CH = 16384 => nrx_bufs = 8

                // for SPIBUF_W = 2048, RX_CHANS = 14, => nrx_samps = 48
			    // 1/(12000/nrx_samps) = interrupt every 4 ms / 250 Hz
                // for RXBUF_SIZE_14CH = 32768 => nrx_bufs = 16

                DEFp    NRX_IQW         3               // 1.5 words (24-bits) per I,Q
                DEFp    NRX_SPI         SPIBUF_W - 1    // can't use last word for some reason
                
                DEFp    NRX_OVHD        3 + 1 + 1   // ticks 3w, count 1w, round up 1w
				DEFp	NRX_SAMPS_RPT	8

				DEFh	USE_RX_CIC24	0

			#if USE_RX_CIC24
				DEFp	RX1_BITS		24
				DEFp	RX2_BITS		23
			#else
				DEFp	RX1_BITS		22
				DEFp	RX2_BITS		18
				//DEFp	RX1_BITS		16
				//DEFp	RX2_BITS		16
			#endif
				DEFp	RXO_BITS		24

				DEFp	RX1_STAGES		3
				DEFp	RX2_STAGES		5
				
				
				// waterfall
				DEFp	MAX_ZOOM		14

				DEFp    NWF_FFT         8192
                DEFp    NWF_IQW         2           // 1 word (16-bits) per I,Q
				DEFp    NWF_NXFER       NWF_FFT * NWF_IQW / SPIBUF_W + 1
				DEFp	NWF_SAMPS		NWF_FFT / NWF_NXFER + 1

				DEFp	NWF_SAMPS_RPT	50
				DEFp	NWF_SAMPS_LOOP	NWF_SAMPS / NWF_SAMPS_RPT
				DEFp	NWF_SAMPS_LOOP2	NWF_SAMPS_LOOP * NWF_SAMPS_RPT
				DEFp	NWF_SAMPS_REM	NWF_SAMPS - NWF_SAMPS_LOOP2
				
				DEFh	USE_WF_1CIC		1
				DEFh	USE_WF_PRUNE	1
				DEFh	USE_WF_CIC24	1
				DEFh	USE_WF_MEM24	0
				DEFh	USE_WF_NEW		0

				DEFp	WF1_STAGES		5
				DEFp	WF2_STAGES		5
				
			#if USE_WF_CIC24
				DEFp	WF1_BITS		24
				DEFp	WF2_BITS		24
			#else
				DEFp	WF1_BITS		16
				DEFp	WF2_BITS		16
			#endif
			
			#if USE_WF_MEM24
				DEFp	WFO_BITS		24
			#else
				DEFp	WFO_BITS		16
			#endif
			
			#if USE_WF_1CIC
				DEFp	WF_1CIC_MAXD	8192
				DEFp	WF_2CIC_MAXD	0			// to keep Vivado happy
			#else
				DEFp	WF_2CIC_MAXD	128			// 8192 = 128 * 64
				DEFp	WF_2CIC_POW2	7
				DEFp	WF_1CIC_MAXD	0			// to keep Vivado happy
			#endif
			
			
				// gps
				DEFp    MAX_GPS_CHANS   12          // limited by ipcore_bram_gps_4k_12b
                DEFp	GPS_CHANS		12

				//DEFp    GPS_INTEG_BITS  16          // width of EPL I/Q integrators
				//DEFp    GPS_INTEG_BITS  18          // width of EPL I/Q integrators
				DEFp    GPS_INTEG_BITS  20          // width of EPL I/Q integrators
				
				DEFp    GPS_REPL_BITS   18          // width of clock replicas
				DEFp	MAX_NAV_BITS	128

			#if STACK_CHECK
			    DEFp    GPS_RPT         8
			#else
			    DEFp    GPS_RPT         32
			#endif
			
				DEFp	GPS_SAMPS		256
				DEFp	GPS_SAMPS_RPT	GPS_RPT
				DEFp	GPS_SAMPS_LOOP	GPS_SAMPS / GPS_SAMPS_RPT

				DEFp	GPS_IQ_SAMPS    255         // not 256 due to SPI buffer edge bug
				DEFp	GPS_IQ_SAMPS_W  GPS_IQ_SAMPS * 4    // *2 = IQ, *2 = 2 words each

				DEFp	L1_CODEBITS     10
				DEFp	L1_CODELEN      1023

				DEFp    E1B_MODE        0x800
				DEFp	E1B_CODEBITS    12
				DEFp	E1B_CODELEN     4092
				DEFp	E1B_CODE_XFERS  1 << E1B_CODEBITS / SPIBUF_W
				DEFp	E1B_CODE_LOOP   E1B_CODELEN / E1B_CODE_XFERS

				DEFp	E1B_CODE_RPT	GPS_RPT
				DEFp	E1B_CODE_LOOP2	E1B_CODE_LOOP / E1B_CODE_RPT
				DEFp	E1B_CODE_LOOP3	E1B_CODE_LOOP2 * E1B_CODE_RPT
				DEFp	E1B_CODE_REM	E1B_CODE_LOOP - E1B_CODE_LOOP3


; ============================================================================

// NB: [10:0] (0x400 max) because [11] is used for further decoding

				// read reg (rdReg & op[10:0], one hot)
				// these 3 must be in these bit positions: see gps.v
				DEFb	GET_CHAN_IQ		0x001
				DEFb	GET_SRQ			0x002
				DEFb	GET_SNAPSHOT	0x004
				
				DEFb	HOST_RX			0x008
				DEFb	GET_RX_SRQ		0x010
				DEFb	GET_CPU_CTR0	0x020
				DEFb	GET_CPU_CTR1	0x040
				DEFb	GET_CPU_CTR2	0x080
				DEFb	GET_CPU_CTR3	0x100
				DEFb	GET_STATUS		0x200
	
				// read reg (rdReg2 & op[10:0], one hot)

				// write reg (wrReg & op[10:0], one hot)
				DEFb	HOST_TX			0x001
				DEFb	SET_MASK		0x002
				DEFb	SET_CHAN		0x004
				DEFb	SET_CG_NCO		0x008
				DEFb	SET_LO_NCO		0x010
				DEFb	SET_SAT			0x020
				DEFb	SET_E1B_CODE    0x040
				DEFb	SET_PAUSE		0x080
				DEFb	SET_CNT_MASK    0x400
				
				// write reg (wrReg2 & op[10:0], one hot)
				DEFb	SET_CTRL		0x001
				DEFb	SET_RX_CHAN		0x002
				DEFb	SET_RX_FREQ		0x004
				DEFb	SET_RX_FREQ_L   0x008
				DEFb	SET_RX_NSAMPS	0x010
				DEFb	SET_GEN			0x020
				DEFb	SET_GEN_ATTN	0x040
				DEFb	SET_WF_FREQ		0x080
				DEFb	SET_WF_DECIM	0x100
				DEFb	SET_WF_CHAN		0x200
				DEFb	WF_SAMPLER_RST	0x400
	
				// events (wrEvt & op[10:0], one hot)
				DEFb	HOST_RST		0x001
				DEFb	HOST_RDY		0x002
				DEFb	GPS_SAMPLER_RST	0x004
				DEFb	GET_GPS_SAMPLES	0x008	// data transfer goes directly to SPI BRAM
				DEFb	GET_MEMORY		0x010   // causes ecpu data memory (with TOS pointer++) to SPI BRAM transfer
				DEFb	GET_LOG			0x020	// data transfer goes directly to SPI BRAM
				DEFb	PUT_LOG			0x040
				DEFb	LOG_RST			0x080

				// events (wrEvt2 & op[10:0], one hot)
				DEFb	GET_RX_SAMP		0x001	// data transfer goes directly to SPI BRAM
				DEFb	RX_BUFFER_RST	0x002
				DEFb	RX_GET_BUF_CTR	0x004	// data transfer goes directly to SPI BRAM
				DEFb	SET_WF_CONTIN	0x008
				DEFb	GET_WF_SAMP_I	0x010	// data transfer goes directly to SPI BRAM
				DEFb	GET_WF_SAMP_Q	0x020	// "
				DEFb	CLR_RX_OVFL		0x040
				DEFb	FREEZE_TOS		0x080
				DEFb	CPU_CTR_CLR		0x100
				DEFb	CPU_CTR_ENA		0x200
				DEFb	CPU_CTR_DIS		0x400


				// WF_SAMPLER_RST
				DEFb	WF_SAMP_RD_RST	0x1
				DEFb	WF_SAMP_WR_RST	0x2
				DEFb	WF_SAMP_CONTIN	0x4
				DEFb	WF_SAMP_SYNC	0x8

				// GET_STATUS
				DEFp	STAT_FPGA_ID	0x000f
				DEFp	STAT_USER       0x00f0
				DEFb	STAT_DNA_DATA	0x0010
				DEFp	STAT_FPGA_VER	0x0f00
				DEFp	STAT_FW_ID		0x7000
				DEFb	STAT_OVFL		0x8000

				// SET_CTRL
				DEFb	CTRL_OSC_EN		0x0100
				DEFb	CTRL_EEPROM_WP	0x0200
				DEFb	CTRL_UNUSED_OUT CTRL_EEPROM_WP
				DEFb	CTRL_USE_GEN	0x0400
				DEFb	CTRL_CMD_READY	0x0800
				DEFb	CTRL_SND_INTR	0x1000
				DEFb	CTRL_DNA_READ	0x2000
				DEFb	CTRL_DNA_SHIFT	0x4000
				DEFb	CTRL_DNA_CLK	0x8000