<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW5A-25A" pn="GW5A-LV25MG121NES">gw5a25a-000</Device>
    <FileList>
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        <File path="src/sirv_1cyc_sram_ctrl.v" type="file.verilog" enable="1"/>
        <File path="src/sirv_AsyncResetReg.v" type="file.verilog" enable="1"/>
        <File path="src/sirv_AsyncResetRegVec.v" type="file.verilog" enable="1"/>
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        <File path="src/sirv_DeglitchShiftRegister.v" type="file.verilog" enable="1"/>
        <File path="src/sirv_LevelGateway.v" type="file.verilog" enable="1"/>
        <File path="src/sirv_ResetCatchAndSync.v" type="file.verilog" enable="1"/>
        <File path="src/sirv_ResetCatchAndSync_2.v" type="file.verilog" enable="1"/>
        <File path="src/sirv_aon.v" type="file.verilog" enable="1"/>
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        <File path="src/sirv_aon_porrst.v" type="file.verilog" enable="1"/>
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        <File path="src/sirv_aon_wrapper.v" type="file.verilog" enable="1"/>
        <File path="src/sirv_clint.v" type="file.verilog" enable="1"/>
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</Project>