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I/O Assignment Analysis report for key
Sat Jun 05 10:32:27 2021
Quartus II 64-Bit Version 11.1 Build 173 11/01/2011 Service Pack 0.11 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. I/O Assignment Analysis Summary
3. Parallel Compilation
4. Fitter Messages
5. I/O Assignment Warnings
6. Incremental Compilation Preservation Summary
7. Incremental Compilation Partition Settings
8. Incremental Compilation Placement Preservation
9. Pin-Out File
10. Fitter Partition Statistics
11. Input Pins
12. Output Pins
13. I/O Bank Usage
14. All Package Pins
15. I/O Rules Summary
16. I/O Rules Details
17. I/O Rules Matrix
18. I/O Assignment Analysis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------+
; I/O Assignment Analysis Summary ;
+--------------------------------+---------------------------------------------------+
; I/O Assignment Analysis Status ; Successful - Sat Jun 05 10:32:27 2021 ;
; Quartus II 64-Bit Version ; 11.1 Build 173 11/01/2011 SP 0.11 SJ Full Version ;
; Revision Name ; key ;
; Top-level Entity Name ; key ;
; Family ; Cyclone IV E ;
; Device ; EP4CE6E22C8 ;
; Timing Models ; Final ;
; Total pins ; 14 / 92 ( 15 % ) ;
; Total virtual pins ; 0 ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+--------------------------------+---------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Fitter
Info: Version 11.1 Build 173 11/01/2011 Service Pack 0.11 SJ Full Version
Info: Processing started: Sat Jun 05 10:32:24 2021
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off key -c key --check_ios
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (119006): Selected device EP4CE6E22C8 for design "key"
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EP4CE10E22C8 is compatible
Info (176445): Device EP4CE15E22C8 is compatible
Info (176445): Device EP4CE22E22C8 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 10 pins of 14 total pins
Info (169086): Pin count[0] not assigned to an exact location on the device
Info (169086): Pin count[1] not assigned to an exact location on the device
Info (169086): Pin count[2] not assigned to an exact location on the device
Info (169086): Pin count[3] not assigned to an exact location on the device
Info (169086): Pin count[4] not assigned to an exact location on the device
Info (169086): Pin count[5] not assigned to an exact location on the device
Info (169086): Pin count[6] not assigned to an exact location on the device
Info (169086): Pin count[7] not assigned to an exact location on the device
Info (169086): Pin count[8] not assigned to an exact location on the device
Info (169086): Pin count[9] not assigned to an exact location on the device
Info (176353): Automatically promoted node clk~input (placed in PIN 24 (CLK2, DIFFCLK_1p))
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 10 (unused VREF, 2.5V VCCIO, 0 input, 10 output, 0 bidirectional)
Info (176212): I/O standards used: 2.5 V.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 7 pins available
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 12 pins available
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 8 pins available
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available
Info (176213): I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used -- 11 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (121043): Results from the I/O assignment analysis compilation cannot be preserved because I/O assignment analysis was run with Incremental Compilation enabled
Info: Quartus II 64-Bit I/O Assignment Analysis was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 4581 megabytes
Info: Processing ended: Sat Jun 05 10:32:27 2021
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:01
+-------------------------------------------------+
; I/O Assignment Warnings ;
+----------+--------------------------------------+
; Pin Name ; Reason ;
+----------+--------------------------------------+
; led ; Missing drive strength and slew rate ;
; count[0] ; Missing drive strength and slew rate ;
; count[1] ; Missing drive strength and slew rate ;
; count[2] ; Missing drive strength and slew rate ;
; count[3] ; Missing drive strength and slew rate ;
; count[4] ; Missing drive strength and slew rate ;
; count[5] ; Missing drive strength and slew rate ;
; count[6] ; Missing drive strength and slew rate ;
; count[7] ; Missing drive strength and slew rate ;
; count[8] ; Missing drive strength and slew rate ;
; count[9] ; Missing drive strength and slew rate ;
+----------+--------------------------------------+
+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+---------------------+------------------------+
; Type ; Value ;
+---------------------+------------------------+
; Placement (by node) ; ;
; -- Requested ; 0 / 79 ( 0.00 % ) ;
; -- Achieved ; 0 / 79 ( 0.00 % ) ;
; ; ;
; Routing (by net) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
; -- Achieved ; 0 / 0 ( 0.00 % ) ;
+---------------------+------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Top ; 69 ; 0 ; N/A ; Source File ;
; hard_block:auto_generated_inst ; 10 ; 0 ; N/A ; Source File ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/fpga_pro/KEY/key.pin.
+----------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics ;
+---------------------------------------------+---------------------+--------------------------------+
; Statistic ; Top ; hard_block:auto_generated_inst ;
+---------------------------------------------+---------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
; Total logic elements ; 29 / 6272 ( < 1 % ) ; 0 / 6272 ( 0 % ) ;
; -- Combinational with no register ; 18 ; 0 ;
; -- Register only ; 0 ; 0 ;
; -- Combinational with a register ; 11 ; 0 ;
; ; ; ;
; Logic element usage by number of LUT inputs ; ; ;
; -- 4 input functions ; 11 ; 0 ;
; -- 3 input functions ; 11 ; 0 ;
; -- <=2 input functions ; 7 ; 0 ;
; -- Register only ; 0 ; 0 ;
; ; ; ;
; Logic elements by mode ; ; ;
; -- normal mode ; 25 ; 0 ;
; -- arithmetic mode ; 4 ; 0 ;
; ; ; ;
; Total registers ; 11 ; 0 ;
; -- Dedicated logic registers ; 11 / 6272 ( < 1 % ) ; 0 / 6272 ( 0 % ) ;
; -- I/O registers ; 0 ; 0 ;
; ; ; ;
; Total LABs: partially or completely used ; 3 / 392 ( < 1 % ) ; 0 / 392 ( 0 % ) ;
; ; ; ;
; Virtual pins ; 0 ; 0 ;
; I/O pins ; 14 ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ;
; Total memory bits ; 0 ; 0 ;
; Total RAM block bits ; 0 ; 0 ;
; ; ; ;
; Connections ; ; ;
; -- Input Connections ; 0 ; 0 ;
; -- Registered Input Connections ; 0 ; 0 ;
; -- Output Connections ; 0 ; 0 ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
; -- Total Connections ; 129 ; 5 ;
; -- Registered Connections ; 33 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
; ; ; ;
; Partition Interface ; ; ;
; -- Input Ports ; 3 ; 0 ;
; -- Output Ports ; 11 ; 0 ;
; -- Bidir Ports ; 0 ; 0 ;
; ; ; ;
; Registered Ports ; ; ;
; -- Registered Input Ports ; 0 ; 0 ;
; -- Registered Output Ports ; 0 ; 0 ;
; ; ; ;
; Port Connectivity ; ; ;
; -- Input Ports driven by GND ; 0 ; 0 ;
; -- Output Ports driven by GND ; 0 ; 0 ;
; -- Input Ports driven by VCC ; 0 ; 0 ;
; -- Output Ports driven by VCC ; 0 ; 0 ;
; -- Input Ports with no Source ; 0 ; 0 ;
; -- Output Ports with no Source ; 0 ; 0 ;
; -- Input Ports with no Fanout ; 0 ; 0 ;
; -- Output Ports with no Fanout ; 0 ; 0 ;
+---------------------------------------------+---------------------+--------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; clk ; 24 ; 2 ; 0 ; 11 ; 14 ; 11 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ;
; key ; 90 ; 6 ; 34 ; 12 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ;
; rst ; 88 ; 5 ; 34 ; 12 ; 21 ; 18 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ;
+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; count[0] ; 38 ; 3 ; 1 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[1] ; 39 ; 3 ; 1 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[2] ; 42 ; 3 ; 3 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[3] ; 43 ; 3 ; 5 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[4] ; 44 ; 3 ; 5 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[5] ; 49 ; 3 ; 13 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[6] ; 50 ; 3 ; 13 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[7] ; 51 ; 3 ; 16 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[8] ; 52 ; 3 ; 16 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; count[9] ; 53 ; 3 ; 16 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ;
; led ; 143 ; 8 ; 1 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+------------------------------------------------------------+
; I/O Bank Usage ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1 ; 4 / 11 ( 36 % ) ; 2.5V ; -- ;
; 2 ; 1 / 8 ( 13 % ) ; 2.5V ; -- ;
; 3 ; 10 / 11 ( 91 % ) ; 2.5V ; -- ;
; 4 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ;
; 5 ; 1 / 13 ( 8 % ) ; 2.5V ; -- ;
; 6 ; 2 / 10 ( 20 % ) ; 2.5V ; -- ;
; 7 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ;
; 8 ; 1 / 12 ( 8 % ) ; 2.5V ; -- ;
+----------+------------------+---------------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 3 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 6 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
; 7 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 8 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
; 9 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
; 10 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 11 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 12 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
; 13 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
; 14 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 15 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 16 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 17 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 18 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 20 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 21 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
; 22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 23 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 24 ; 25 ; 2 ; clk ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
; 25 ; 26 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 26 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 28 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 29 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 30 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 31 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 32 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 33 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 34 ; 41 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 35 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 36 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 37 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 38 ; 45 ; 3 ; count[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 39 ; 46 ; 3 ; count[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 40 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 41 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 42 ; 52 ; 3 ; count[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 43 ; 53 ; 3 ; count[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 44 ; 54 ; 3 ; count[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 45 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 46 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 47 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 48 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 49 ; 68 ; 3 ; count[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 50 ; 69 ; 3 ; count[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 51 ; 70 ; 3 ; count[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 52 ; 72 ; 3 ; count[8] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 53 ; 73 ; 3 ; count[9] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
; 54 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 55 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 56 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 57 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 58 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 59 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 60 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 61 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 63 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 64 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 65 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 66 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 67 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 68 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 69 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 70 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 71 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 72 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 73 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 74 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 75 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 76 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 77 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 78 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 81 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 82 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 83 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 84 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 85 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 86 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 87 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 88 ; 125 ; 5 ; rst ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
; 89 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 90 ; 127 ; 6 ; key ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
; 91 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 92 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
; 93 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 94 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
; 95 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 96 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 97 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
; 97 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
; 98 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 99 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 100 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 101 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
; 102 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 103 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 104 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 105 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 106 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 107 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 108 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 109 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 110 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 111 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 112 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 113 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 114 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 115 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 116 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 117 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 118 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 119 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 120 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 121 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 122 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 123 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 124 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 125 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 126 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 127 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 128 ; 177 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 129 ; 178 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 130 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 131 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 132 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 133 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 134 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 135 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 136 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 137 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 138 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 139 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 141 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 142 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 143 ; 202 ; 8 ; led ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
; 144 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; EPAD ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+------------------------------------------+
; I/O Rules Summary ;
+----------------------------------+-------+
; I/O Rules Statistic ; Total ;
+----------------------------------+-------+
; Total I/O Rules ; 30 ;
; Number of I/O Rules Passed ; 12 ;
; Number of I/O Rules Failed ; 0 ;
; Number of I/O Rules Unchecked ; 0 ;
; Number of I/O Rules Inapplicable ; 18 ;
+----------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass ; 4 ; 0 ; 4 ; 0 ; 0 ; 14 ; 4 ; 0 ; 14 ; 14 ; 0 ; 11 ; 0 ; 0 ; 3 ; 0 ; 11 ; 3 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 10 ; 14 ; 10 ; 14 ; 14 ; 0 ; 10 ; 14 ; 0 ; 0 ; 14 ; 3 ; 14 ; 14 ; 11 ; 14 ; 3 ; 11 ; 14 ; 14 ; 14 ; 3 ; 14 ; 14 ; 14 ; 14 ; 14 ; 0 ; 14 ; 14 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; led ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; count[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; rst ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; clk ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; key ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+----------------------------------+
; I/O Assignment Analysis Messages ;
+----------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Fitter
Info: Version 11.1 Build 173 11/01/2011 Service Pack 0.11 SJ Full Version
Info: Processing started: Sat Jun 05 10:32:24 2021
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off key -c key --check_ios
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (119006): Selected device EP4CE6E22C8 for design "key"
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EP4CE10E22C8 is compatible
Info (176445): Device EP4CE15E22C8 is compatible
Info (176445): Device EP4CE22E22C8 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 10 pins of 14 total pins
Info (169086): Pin count[0] not assigned to an exact location on the device
Info (169086): Pin count[1] not assigned to an exact location on the device
Info (169086): Pin count[2] not assigned to an exact location on the device
Info (169086): Pin count[3] not assigned to an exact location on the device
Info (169086): Pin count[4] not assigned to an exact location on the device
Info (169086): Pin count[5] not assigned to an exact location on the device
Info (169086): Pin count[6] not assigned to an exact location on the device
Info (169086): Pin count[7] not assigned to an exact location on the device
Info (169086): Pin count[8] not assigned to an exact location on the device
Info (169086): Pin count[9] not assigned to an exact location on the device
Info (176353): Automatically promoted node clk~input (placed in PIN 24 (CLK2, DIFFCLK_1p))
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 10 (unused VREF, 2.5V VCCIO, 0 input, 10 output, 0 bidirectional)
Info (176212): I/O standards used: 2.5 V.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 7 pins available
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 12 pins available
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 8 pins available
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available
Info (176213): I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used -- 11 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (121043): Results from the I/O assignment analysis compilation cannot be preserved because I/O assignment analysis was run with Incremental Compilation enabled
Info: Quartus II 64-Bit I/O Assignment Analysis was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 4581 megabytes
Info: Processing ended: Sat Jun 05 10:32:27 2021
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:01
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