diff --git a/arm_mps2_an386/liteos_m/config.gni b/arm_mps2_an386/liteos_m/config.gni index 04d93eea5455f47c8a30af4b10b6dc508ae65c66..8b4ceb3aef862727b06b3749b2b40dfaaa461901 100644 --- a/arm_mps2_an386/liteos_m/config.gni +++ b/arm_mps2_an386/liteos_m/config.gni @@ -19,6 +19,7 @@ kernel_version = "3.0.0" # Board CPU type, e.g. "cortex-a7", "riscv32". board_cpu = "cortex-m4" +target_cpu= "arm" # Board arch, e.g. "armv7-a", "rv32imac". board_arch = "" @@ -40,7 +41,9 @@ board_toolchain_prefix = "arm-none-eabi-" board_toolchain_type = "gcc" #Debug compiler optimization level options -board_opt_flags = [] +board_opt_flags = [ + "-O2", +] # Board related common compile flags. board_cflags = [ @@ -52,7 +55,6 @@ board_cflags = [ "-fno-strict-aliasing", "-fsigned-char", "-std=c99", - "-O2", "-DUSE_HAL_DRIVER", "-D__LITEOS_M__", ] @@ -62,7 +64,6 @@ board_asmflags = [ "-mcpu=cortex-m4", "-mthumb", "-static", - "-O2", ] board_asmflags += board_opt_flags diff --git a/arm_mps2_an386_clang/BUILD.gn b/arm_mps2_an386_clang/BUILD.gn new file mode 100644 index 0000000000000000000000000000000000000000..67a60568c41012dc17df5681dd29011d19047e6c --- /dev/null +++ b/arm_mps2_an386_clang/BUILD.gn @@ -0,0 +1,31 @@ +# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. +# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +group("arm_mps2_an386_clang") { +} diff --git a/arm_mps2_an386_clang/README.md b/arm_mps2_an386_clang/README.md new file mode 100644 index 0000000000000000000000000000000000000000..805ff74bcf1b7f21f2734ac217bc005f13cf251a --- /dev/null +++ b/arm_mps2_an386_clang/README.md @@ -0,0 +1,141 @@ +### Qemu Arm Cortex-m4 mps2-an386 HOWTO + +#### 1. Brief introduction +`arm_mps2_an386/` subdirectory contains part of the OpenHarmony LiteOS demonstration support for Qemu Arm Cortex-m4 mps2-an386 Platform, +here called *arm_mps2_an386*. +cortex-m4 Virtual platform is a `qemu-system-arm` machine target that provides emulation +for a generic, arm-based board. + +Introduced functionality adds support for Cortex-m4 (1 CPU with security extensions), 16MB memory virtual platform. + +Note: System memory size is hard-coded to 16MB. + +#### 2. Setting up environment + +[Setting up a development environment](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/quick-start/quickstart-lite-env-setup.md) + +Compiler install + +1.Command to install + +Note: Command to install toolchain without arm-none-eabi-gdb, gdb cannot be debugged. + +``` +sudo apt install gcc-arm-none-eabi +``` + +2.The installation package to install + +Note: If you have already passed the command to install gcc-arm-none-eabi, can through the command: `sudo apt remove +gcc-arm-none-eabi` after unloading, install again. + +Download toolchain: [package](https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/6-2017q2/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2)。 + +``` +chmod 777 gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 +tar -xvf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 install_path +``` + +Add the installation path to the environment variable: + +``` +vim ~/.bashrc +``` + +Add the following command line to the last line of ~/.bashrc: + +``` +export PATH=$PATH:install_path/gcc-arm-none-eabi-6-2017-q2-update/bin +``` + +#### 3. Code acquisition + +[Code acquisition](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/get-code/sourcecode-acquire.md) + +Note: One can use `repo` to fetch code in a straightforward manner. + +#### 4. Building from sources + +In the root directory of the obtained source code, run the following command: + +``` +hb set +``` + +Select `qemu_mini_system_demo` under **ohemu**. + +Run the following build command: +``` +hb build -f +``` + +This will build `OHOS_Image` for Qemu Cortex-m4 mps2-an386 machine. + + +After build is finished, the resulting image can be found in: +``` +out/arm_mps2_an386/qemu_mini_system_demo/ +``` +#### 5. Running image in Qemu + +a) If not installed, please install `qemu-system-arm` +For details, please refer to the HOWTO: [Qemu installation](https://gitee.com/openharmony/device_qemu/blob/HEAD/README.md) + +b) Run + +Run the `./qemu-run --help` command. The following information is displayed: + +``` +Usage: qemu-run [OPTION]... +Run a OHOS image in qemu according to the options. + + Options: + + -e, --exec file_name kernel exec file name + -n, --net-enable enable net + -g, --gdb enable gdb for kernel + -t, --test test mode, exclusive with -g + -h, --help print help info + + By default, the kernel exec file is: out/arm_mps2_an386/qemu_mini_system_demo/OHOS_Image. +``` + +#### 6. gdb debug + +``` +cd device/qemu/arm_mps2_an386 +vim liteos_m/config.gni +``` + +In the modified `board_opt_flags` compiler options: + +``` +board_opt_flags = [] +``` +to: + +``` +board_opt_flags = [ "-g" ] +``` + +Save and exit, recompile under OHOS root directory: + +``` +hb build -f +``` + +In a window to enter the command: + +``` +./qemu-run -g +``` + +In another window to enter the command: + +``` +arm-none-eabi-gdb out/arm_mps2_an386/qemu_mini_system_demo/OHOS_Image +(gdb) target remote localhost:1234 +(gdb) b main +``` + +More GDB related debugging can refer to [GDB instruction manual](https://sourceware.org/gdb/current/onlinedocs/gdb). diff --git a/arm_mps2_an386_clang/README_zh.md b/arm_mps2_an386_clang/README_zh.md new file mode 100644 index 0000000000000000000000000000000000000000..996229ef88c12a717958179a11035f6b3400b768 --- /dev/null +++ b/arm_mps2_an386_clang/README_zh.md @@ -0,0 +1,138 @@ +# Qemu Arm Cortex-m4 mps2-an386 教程 + +## 1. 简介 +`arm_mps2_an386/` 子目录包含部分Qemu arn cortex-m4虚拟化平台验证的OpenHarmony kernel\_liteos\_m的代码，目录名为*arm_mps2_an386*。 +Arm Cortex-m4 虚拟化平台是一个 `qemu-system-arm` 的目标设备，通过它来模拟一个通用的、基于arm cortex-m4架构的单板。 + +这次模拟的配置是：arm cortex-m4架构，1个CPU，16M内存。 + +提示: 系统内存硬编码为16MB。 + +## 2. 环境搭建 + +[环境搭建](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/quick-start/quickstart-lite-env-setup.md) + +编译器安装 + +1.命令安装 + +提示：命令安装的工具链无 arm-none-eabi-gdb，无法进行gdb调试 + +``` +sudo apt install gcc-arm-none-eabi +``` + +2.安装包安装 + +提示：如果已经通过命令安装了gcc-arm-none-eabi， 可以通过命令：`sudo apt remove gcc-arm-none-eabi` 卸载之后，再进行安装。 + +下载工具链[安装包](https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/6-2017q2/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2)。 + +``` +chmod 777 gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 +tar -xvf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 install_path +``` + +将安装路径添加到环境变量中: + +``` +vim ~/.bashrc +``` + +在~/.bashrc最末尾加入: + +``` +export PATH=$PATH:install_path/gcc-arm-none-eabi-6-2017-q2-update/bin +``` + +## 3. 获取源码 + +[代码获取](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/get-code/sourcecode-acquire.md) + +提示: 可以使用 `repo` 命令来获取源码。 + +## 4. 源码构建 + +在已经获取的源码根目录，请输入： + +``` +hb set +``` + +选择ohemu下的`qemu_mini_system_demo`选项。 + + +然后执行构建命令如下： +``` +hb build -f +``` + +这个命令构建会产生 `OHOS_Image` 的镜像文件。 + +在构建完成之后，对应的镜像文件在如下目录： +``` +out/arm_mps2_an386/qemu_mini_system_demo/ +``` +## 5. 在Qemu中运行镜像 + +a) 如果没有安装 `qemu-system-arm` ，安装请参考链接:[Qemu安装指导](https://gitee.com/openharmony/device_qemu/blob/HEAD/README_zh.md) + +b) 运行 + +执行`./qemu-run --help`提示如下： + +``` +Usage: qemu-run [OPTION]... +Run a OHOS image in qemu according to the options. + + Options: + + -e, --exec file_name kernel exec file name + -n, --net-enable enable net + -g, --gdb enable gdb for kernel + -t, --test test mode, exclusive with -g + -h, --help print help info + + By default, the kernel exec file is: out/arm_mps2_an386/qemu_mini_system_demo/OHOS_Image. +``` + +## 6. gdb调试 + +``` +cd device/qemu/arm_mps2_an386 +vim liteos_m/config.gni +``` + +将 `board_opt_flags` 中的 + +``` +board_opt_flags = [] +``` + +编译选项修改为: + +``` +board_opt_flags = [ "-g" ] +``` + +保存并退出，在OHOS根目录重新编译: + +``` +hb build -f +``` + +在一个窗口中输入命令： + +``` +./qemu-run -g +``` + +在另一个窗口中输入命令： + +``` +arm-none-eabi-gdb out/arm_mps2_an386/qemu_mini_system_demo/OHOS_Image +(gdb) target remote localhost:1234 +(gdb) b main +``` + +更多gdb相关的调试可以查阅：[gdb指导手册](https://sourceware.org/gdb/current/onlinedocs/gdb)。 diff --git a/arm_mps2_an386_clang/liteos_m/BUILD.gn b/arm_mps2_an386_clang/liteos_m/BUILD.gn new file mode 100644 index 0000000000000000000000000000000000000000..76ab3652f69b1a700f2fa4b35ef5834b92ddb99d --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/BUILD.gn @@ -0,0 +1,36 @@ +# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. +# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +group("liteos_m") { + deps = [ "board" ] +} + +config("public") { + configs = [ "board:public" ] +} diff --git a/arm_mps2_an386_clang/liteos_m/board/BUILD.gn b/arm_mps2_an386_clang/liteos_m/board/BUILD.gn new file mode 100644 index 0000000000000000000000000000000000000000..87da20cdea546fe86fe76e95449cd08597e70b73 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/BUILD.gn @@ -0,0 +1,81 @@ +# Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import("//kernel/liteos_m/liteos.gni") + +module_name = "bsp_config" + +kernel_module(module_name) { + asmflags = board_asmflags + + sources = [ + "driver/arm_uart_drv.c", + "driver/net/lan9118_eth_drv.c", + "driver/uart.c", + "fs/ff_gen_drv.c", + "libc/dprintf.c", + "main.c", + "startup.s", + ] + deps = [ "//device/qemu/arm_mps2_an386/liteos_m/board/fs:fs_adapter" ] + include_dirs = [ "//device/qemu/arm_mps2_an386/liteos_m/board/fs" ] + if (!defined(LOSCFG_TEST)) { + # kernel's testsuites not enabled, use ower's + sources += [ "test/test_demo.c" ] + } + include_dirs += [ "driver/net/" ] +} + +config("public") { + include_dirs = [ + ".", + "include", + "fs", + "driver", + ] + ldflags = [ + "-nostartfiles", + "-Wl,-T" + rebase_path("liteos.ld"), + "-nostdlib", + ] + + libs = [ + "clang_rt.builtins", + #"nosys", + #"gcc", + ] + + if (defined(LOSCFG_LIBC_NEWLIB)) { + ldflags -= [ "-nostdlib" ] + libs -= [ "nosys" ] + libs += [ + "c", + "m", + ] + } +} diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/LICENSE-apache-2.0.txt b/arm_mps2_an386_clang/liteos_m/board/driver/LICENSE-apache-2.0.txt new file mode 100644 index 0000000000000000000000000000000000000000..0cdd12c725f44017d075f4585ccb35139bc5f612 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/LICENSE-apache-2.0.txt @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. \ No newline at end of file diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/arm_uart_drv.c b/arm_mps2_an386_clang/liteos_m/board/driver/arm_uart_drv.c new file mode 100644 index 0000000000000000000000000000000000000000..e51664be5278e7023cc0ecfefc4c817c638cc22f --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/arm_uart_drv.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2016-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_uart_drv.h" + +#include + +/* UART register map structure */ +struct _arm_uart_reg_map_t { + volatile uint32_t data; /* Offset: 0x000 (R/W) data register */ + volatile uint32_t state; /* Offset: 0x004 (R/W) status register */ + volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ + union { + volatile uint32_t intrstatus; /* Offset: 0x00c (R/ ) interrupt status + * register */ + volatile uint32_t intrclear; /* Offset: 0x00c ( /W) interrupt clear + * register */ + }intr_reg; + volatile uint32_t bauddiv; /* Offset: 0x010 (R/W) Baudrate divider + * register */ +}; + +/* CTRL Register */ +#define ARM_UART_TX_EN (1ul << 0) +#define ARM_UART_RX_EN (1ul << 1) +#define ARM_UART_TX_INTR_EN (1ul << 2) +#define ARM_UART_RX_INTR_EN (1ul << 3) + +/* STATE Register */ +#define ARM_UART_TX_BF (1ul << 0) +#define ARM_UART_RX_BF (1ul << 1) + +/* INTSTATUS Register */ +#define ARM_UART_TX_INTR (1ul << 0) +#define ARM_UART_RX_INTR (1ul << 1) + +/* UART state definitions */ +#define ARM_UART_INITIALIZED (1ul << 0) + +enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev, + uint32_t system_clk) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + if(system_clk == 0) { + return ARM_UART_ERR_INVALID_ARG; + } + + /* Sets baudrate and system clock */ + dev->data->system_clk = system_clk; + dev->data->baudrate = dev->cfg->default_baudrate; + + /* Sets baudrate */ + p_uart->bauddiv = (dev->data->system_clk / dev->cfg->default_baudrate); + + /* Enables receiver and transmitter */ + p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN; + + dev->data->state = ARM_UART_INITIALIZED; + + return ARM_UART_ERR_NONE; +} + +enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev, + uint32_t baudrate) +{ + uint32_t bauddiv; + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(baudrate == 0) { + return ARM_UART_ERR_INVALID_BAUD; + } + + if(!(dev->data->state & ARM_UART_INITIALIZED)) { + return ARM_UART_ERR_NOT_INIT; + } + + /* Sets baudrate */ + bauddiv = (dev->data->system_clk / baudrate); + dev->data->baudrate = baudrate; + + /* Minimum bauddiv value */ + if(bauddiv < 16) { + return ARM_UART_ERR_INVALID_BAUD; + } + + p_uart->bauddiv = bauddiv; + + return ARM_UART_ERR_NONE; +} + +uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev) +{ + return dev->data->baudrate; +} + +enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev, + uint32_t system_clk) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(system_clk == 0) { + return ARM_UART_ERR_INVALID_ARG; + } + + if(!(dev->data->state & ARM_UART_INITIALIZED)) { + return ARM_UART_ERR_NOT_INIT; + } + + /* Sets system clock */ + dev->data->system_clk = system_clk; + + /* Updates baudrate divider */ + p_uart->bauddiv = (dev->data->system_clk / dev->data->baudrate); + + /* Enables receiver and transmitter */ + return ARM_UART_ERR_NONE; +} + +enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + if(!(p_uart->state & ARM_UART_RX_BF)) { + return ARM_UART_ERR_NOT_READY; + } + + /* Reads data */ + *byte = (uint8_t)p_uart->data; + + return ARM_UART_ERR_NONE; +} + +enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(p_uart->state & ARM_UART_TX_BF) { + return ARM_UART_ERR_NOT_READY; + } + + /* Sends data */ + p_uart->data = byte; + + return ARM_UART_ERR_NONE; +} + +enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & ARM_UART_INITIALIZED)) { + return ARM_UART_ERR_NOT_INIT; + } + + p_uart->ctrl |= ARM_UART_TX_INTR_EN; + + return ARM_UART_ERR_NONE; +} + +void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(dev->data->state & ARM_UART_INITIALIZED ) { + p_uart->ctrl &= ~ARM_UART_TX_INTR_EN; + } +} + +uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & ARM_UART_INITIALIZED)) { + return 0; + } + + return !(p_uart->state & ARM_UART_TX_BF); +} + +enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & ARM_UART_INITIALIZED)) { + return ARM_UART_ERR_NOT_INIT; + } + + p_uart->ctrl |= ARM_UART_RX_INTR_EN; + + return ARM_UART_ERR_NONE; +} + +void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(dev->data->state & ARM_UART_INITIALIZED) { + p_uart->ctrl &= ~ARM_UART_RX_INTR_EN; + } +} + +uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & ARM_UART_INITIALIZED)) { + return 0; + } + + return (p_uart->state & ARM_UART_RX_BF); +} + +void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev, + enum arm_uart_irq_t irq) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + + if(dev->data->state & ARM_UART_INITIALIZED) { + /* Clears pending interrupts */ + switch(irq) { + case ARM_UART_IRQ_RX: + p_uart->intr_reg.intrclear = ARM_UART_RX_INTR; + break; + case ARM_UART_IRQ_TX: + p_uart->intr_reg.intrclear = ARM_UART_TX_INTR; + break; + case ARM_UART_IRQ_COMBINED: + p_uart->intr_reg.intrclear = (ARM_UART_RX_INTR | ARM_UART_TX_INTR); + break; + case ARM_UART_IRQ_NONE: + break; + /* default: not defined to force all cases to be handled */ + } + } +} + +enum arm_uart_irq_t arm_uart_get_interrupt_status(struct arm_uart_dev_t* dev) +{ + struct _arm_uart_reg_map_t* p_uart = + (struct _arm_uart_reg_map_t*)dev->cfg->base; + enum arm_uart_irq_t intrstatus = ARM_UART_IRQ_NONE; + + + if(dev->data->state & ARM_UART_INITIALIZED) { + switch(p_uart->intr_reg.intrstatus) { + case ARM_UART_TX_INTR: + intrstatus = ARM_UART_IRQ_TX; + break; + case ARM_UART_RX_INTR: + intrstatus = ARM_UART_IRQ_RX; + break; + case ARM_UART_TX_INTR | ARM_UART_RX_INTR: + intrstatus = ARM_UART_IRQ_COMBINED; + break; + default: + break; + } + } + + return intrstatus; +} \ No newline at end of file diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/arm_uart_drv.h b/arm_mps2_an386_clang/liteos_m/board/driver/arm_uart_drv.h new file mode 100644 index 0000000000000000000000000000000000000000..729a80601404658860bf90472870bfbc12a06a4f --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/arm_uart_drv.h @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2016-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file arm_uart_drv.h + * \brief Generic driver for ARM UART. + */ + +#ifndef __ARM_UART_DRV_H__ +#define __ARM_UART_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* ARM UART device configuration structure */ +struct arm_uart_dev_cfg_t { + const uint32_t base; /*!< UART base address */ + const uint32_t default_baudrate; /*!< Default baudrate */ +}; + +/* ARM UART device data structure */ +struct arm_uart_dev_data_t { + uint32_t state; /*!< Indicates if the uart driver + is initialized and enabled */ + uint32_t system_clk; /*!< System clock */ + uint32_t baudrate; /*!< Baudrate */ +}; + +/* ARM UART device structure */ +struct arm_uart_dev_t { + const struct arm_uart_dev_cfg_t* cfg; /*!< UART configuration */ + struct arm_uart_dev_data_t* data; /*!< UART data */ +}; + +/* ARM UART enumeration types */ +enum arm_uart_error_t { + ARM_UART_ERR_NONE = 0, /*!< No error */ + ARM_UART_ERR_INVALID_ARG, /*!< Error invalid input argument */ + ARM_UART_ERR_INVALID_BAUD, /*!< Invalid baudrate */ + ARM_UART_ERR_NOT_INIT, /*!< Error UART not initialized */ + ARM_UART_ERR_NOT_READY, /*!< Error UART not ready */ +}; + +enum arm_uart_irq_t { + ARM_UART_IRQ_RX, /*!< RX interrupt source */ + ARM_UART_IRQ_TX, /*!< TX interrupt source */ + ARM_UART_IRQ_COMBINED, /*!< RX-TX combined interrupt source */ + ARM_UART_IRQ_NONE = 0xFF /*!< RX-TX combined interrupt source */ +}; + +/** + * \brief Initializes UART. It uses the default baudrate to configure + * the peripheral at this point. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * \param[in] system_clk System clock used by the device. + * + * \return Returns error code as specified in \ref arm_uart_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev, + uint32_t system_clk); + +/** + * \brief Sets the UART baudrate. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * \param[in] baudrate New baudrate. + * + * \return Returns error code as specified in \ref arm_uart_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev, + uint32_t baudrate); + +/** + * \brief Gets the UART baudrate. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \return Returns the UART baudrate. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev); + +/** + * \brief Sets system clock. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * \param[in] system_clk System clock used by the device. + * + * \return Returns error code as specified in \ref arm_uart_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev, + uint32_t system_clk); +/** + * \brief Reads one byte from UART dev. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * \param[in] byte Pointer to byte. + * + * \return Returns error code as specified in \ref arm_uart_error_t + * + * \note For better performance, this function doesn't check if dev and byte + * pointer are NULL, and if the driver is initialized. + */ +enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte); + +/** + * \brief Writes a byte to UART dev. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * \param[in] byte Byte to write. + * + * \return Returns error code as specified in \ref arm_uart_error_t + * + * \note For better performance, this function doesn't check if dev is NULL and + * if the driver is initialized to have better performance. + */ +enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte); + +/** + * \brief Enables TX interrupt. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \return Returns error code as specified in \ref arm_uart_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev); + +/** + * \brief Disables TX interrupt. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev); + +/** + * \brief Verifies if Tx is ready to send more data. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \return 1 if TX is ready, 0 otherwise. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev); + +/** + * \brief Enables RX interrupt. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \return Returns error code as specified in \ref arm_uart_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev); + +/** + * \brief Disables RX interrupt + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev); + +/** + * \brief Verifies if Rx has data. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \return 1 if RX has data, 0 otherwise. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev); + +/** + * \brief Clears UART interrupt. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * \param[in] irq IRQ source to clean \ref arm_uart_irq_t + * + * \note This function doesn't check if dev is NULL. + */ +void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev, + enum arm_uart_irq_t irq); + +/** + * \brief Returns UART interrupt status. + * + * \param[in] dev UART device struct \ref arm_uart_dev_t + * + * \return IRQ status \ref arm_uart_irq_t + * + * \note This function doesn't check if dev is NULL. + */ +enum arm_uart_irq_t arm_uart_get_interrupt_status(struct arm_uart_dev_t* dev); + +#ifdef __cplusplus +} +#endif +#endif /* __ARM_UART_DRV_H__ */ \ No newline at end of file diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/flash/BUILD.gn b/arm_mps2_an386_clang/liteos_m/board/driver/flash/BUILD.gn new file mode 100644 index 0000000000000000000000000000000000000000..90302096fd4e18b8ca053fbc7ec9b41551a6e43f --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/flash/BUILD.gn @@ -0,0 +1,35 @@ +# Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +static_library("flash") { + sources = [ "ram_virt_flash.c" ] + include_dirs = [ + "//kernel/liteos_m/kernel/include", + "//kernel/liteos_m/kernel/arch/include", + ] +} diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/flash/ram_virt_flash.c b/arm_mps2_an386_clang/liteos_m/board/driver/flash/ram_virt_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..3f52644ef2964b5d3cfe4221c82974fefde64575 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/flash/ram_virt_flash.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "stdio.h" +#include "pthread.h" +#include "securec.h" +#include "los_interrupt.h" +#include "ram_virt_flash.h" + +/* Logic partition on flash devices, if open at the same time, needed modify by user */ +HalLogicPartition g_halPartitions[] = { + [FLASH_PARTITION_DATA0] = { + .partitionDescription = "littlefs", + .partitionStartAddr = 0x21800000, + .partitionLength = 0x800000, // size is 8M + }, + [FLASH_PARTITION_DATA1] = { + .partitionDescription = "vfat", + .partitionStartAddr = 0x21800000, + .partitionLength = 0x800000, // size is 8M + }, +}; + +HalLogicPartition *getPartitionInfo(VOID) +{ + return g_halPartitions; +} + +INT32 virt_flash_erase(HalPartition pdrv, UINT32 offSet, UINT32 size) +{ + UINT32 startAddr = offSet; + UINT32 partitionEnd; + + partitionEnd = g_halPartitions[pdrv].partitionStartAddr + g_halPartitions[pdrv].partitionLength; + if (startAddr >= partitionEnd) { + printf("flash over erase, 0x%x, 0x%x\r\n", startAddr, partitionEnd); + printf("flash over write\r\n"); + return -1; + } + if ((startAddr + size) > partitionEnd) { + size = partitionEnd - startAddr; + printf("flash over write, new len is %d\r\n", size); + } + + UINT32 intSave = LOS_IntLock(); + (VOID)memset_s((VOID *)startAddr, size, 0, size); + LOS_IntRestore(intSave); + return 0; +} + +INT32 virt_flash_write(HalPartition pdrv, UINT32 *offSet, const VOID *buf, UINT32 bufLen) +{ + UINT32 startAddr = *offSet; + UINT32 partitionEnd; + + partitionEnd = g_halPartitions[pdrv].partitionStartAddr + g_halPartitions[pdrv].partitionLength; + if (startAddr >= partitionEnd) { + printf("flash over write, 0x%x, 0x%x\r\n", startAddr, partitionEnd); + return -1; + } + if ((startAddr + bufLen) > partitionEnd) { + bufLen = partitionEnd - startAddr; + printf("flash over write, new len is %d\r\n", bufLen); + } + + UINT32 intSave = LOS_IntLock(); + (VOID)memcpy_s((VOID *)startAddr, bufLen, buf, bufLen); + LOS_IntRestore(intSave); + + return 0; +} + +INT32 virt_flash_erase_write(HalPartition pdrv, UINT32 *offSet, const VOID *buf, UINT32 bufLen) +{ + UINT32 startAddr = *offSet; + UINT32 partitionEnd; + + partitionEnd = g_halPartitions[pdrv].partitionStartAddr + g_halPartitions[pdrv].partitionLength; + if (startAddr >= partitionEnd) { + printf("flash over e&w, 0x%x, 0x%x\r\n", startAddr, partitionEnd); + return -1; + } + if ((startAddr + bufLen) > partitionEnd) { + bufLen = partitionEnd - startAddr; + printf("flash over erase&write, new len is %d\r\n", bufLen); + } + + UINT32 intSave = LOS_IntLock(); + (VOID)memset_s((VOID *)startAddr, bufLen, 0, bufLen); + (VOID)memcpy_s((VOID *)startAddr, bufLen, buf, bufLen); + LOS_IntRestore(intSave); + return 0; +} + +INT32 virt_flash_read(HalPartition pdrv, UINT32 *offSet, VOID *buf, UINT32 bufLen) +{ + UINT32 startAddr = *offSet; + UINT32 partitionEnd; + + partitionEnd = g_halPartitions[pdrv].partitionStartAddr + g_halPartitions[pdrv].partitionLength; + if (startAddr >= partitionEnd) { + printf("flash over read, 0x%x, 0x%x\r\n", startAddr, partitionEnd); + return -1; + } + if ((startAddr + bufLen) > partitionEnd) { + bufLen = partitionEnd - startAddr; + printf("flash over read, new len is %d\r\n", bufLen); + } + + UINT32 intSave = LOS_IntLock(); + (VOID)memcpy_s(buf, bufLen, (VOID *)startAddr, bufLen); + LOS_IntRestore(intSave); + return 0; +} diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/flash/ram_virt_flash.h b/arm_mps2_an386_clang/liteos_m/board/driver/flash/ram_virt_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..c10d10d90228e3b31ab0f9add1a605306d0767d5 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/flash/ram_virt_flash.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RAM_VIRT_FLASH_H_ +#define _RAM_VIRT_FLASH_H_ + +#include "los_compiler.h" +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + FLASH_PARTITION_DATA0 = 0, + FLASH_PARTITION_DATA1 = 1, + FLASH_PARTITION_MAX, +} HalPartition; + +typedef struct { + const CHAR *partitionDescription; + UINT32 partitionStartAddr; + UINT32 partitionLength; + UINT32 partitionOptions; +} HalLogicPartition; + + +HalLogicPartition *getPartitionInfo(VOID); +INT32 virt_flash_erase(HalPartition in_partition, UINT32 off_set, UINT32 size); +INT32 virt_flash_write(HalPartition in_partition, UINT32 *off_set, const VOID *in_buf, UINT32 in_buf_len); +INT32 virt_flash_erase_write(HalPartition in_partition, UINT32 *off_set, const VOID *in_buf, UINT32 in_buf_len); +INT32 virt_flash_read(HalPartition in_partition, UINT32 *off_set, VOID *out_buf, UINT32 in_buf_len); + +#ifdef __cplusplus +} +#endif + +#endif /* _RAM_VIRT_FLASH_H_ */ \ No newline at end of file diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/net/lan9118_eth_drv.c b/arm_mps2_an386_clang/liteos_m/board/driver/net/lan9118_eth_drv.c new file mode 100644 index 0000000000000000000000000000000000000000..64a66132719707769ea433f70f30ad2ba02f1a1e --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/net/lan9118_eth_drv.c @@ -0,0 +1,1266 @@ +/* + * Copyright (c) 2016-2019 Arm Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lan9118_eth_drv.h" +#include "los_debug.h" + +#if LWIP_IPV6 +#include "lwip/ethip6.h" +#endif + +#define DSB __DSB() + +#define LAN9118_NETIF_NAME "lan9118" +#define LAN9118_NETIF_NICK "eth0" +#define LAN9118_NETIF_TEST_IP "10.0.2.15" +#define LAN9118_NETIF_TEST_GW "10.0.2.2" +#define LAN9118_NETIF_TEST_MASK "255.255.255.0" + +#define LAN9118_ETH_MAX_FRAME_SIZE 1522U +#define LAN9118_BUFF_ALIGNMENT 4U +#define UINT32_MAX ((uint32_t)-1) +#define SLEEP_TIME_MS 60 +#define NETIF_SETUP_OVERTIME 100 + +static struct netif g_NetIf; +static const struct lan9118_eth_dev_cfg_t LAN9118_ETH_DEV_CFG = {.base = LAN9118_BASE}; +static struct lan9118_eth_dev_data_t LAN9118_ETH_DEV_DATA = {.state = 0}; +struct lan9118_eth_dev_t LAN9118_ETH_DEV = {&(LAN9118_ETH_DEV_CFG), &(LAN9118_ETH_DEV_DATA)}; +struct lan9118_eth_dev_t* g_dev = &LAN9118_ETH_DEV; + +extern void tcpip_init(tcpip_init_done_fn initfunc, void* arg); + +/** Setter bit manipulation macro */ +#define SET_BIT(WORD, BIT_INDEX) \ + ({ \ + DSB; \ + ((WORD)) |= ((1U) << (BIT_INDEX)); \ + }) + +/** Clearing bit manipulation macro */ +#define CLR_BIT(WORD, BIT_INDEX) \ + ({ \ + DSB; \ + (WORD) &= ~((1U) << (BIT_INDEX)); \ + }) + +/** Getter bit manipulation macro */ +#define GET_BIT(WORD, BIT_INDEX) \ + ({ \ + UINT32 r = (bool)(((WORD) & ((1U) << (BIT_INDEX)))); \ + DSB; \ + r; \ + }) + +/** Setter bit-field manipulation macro */ +#define SET_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET, VALUE) \ + ({ \ + DSB; \ + ((WORD) |= (((VALUE) & (BIT_MASK)) << (BIT_OFFSET))); \ + }) + +/** Clearing bit-field manipulation macro */ +#define CLR_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET, VALUE) \ + ({ \ + DSB; \ + ((WORD) &= ~(((VALUE) & (BIT_MASK)) << (BIT_OFFSET))); \ + }) + +/** Getter bit-field manipulation macro */ +#define GET_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET) \ + ({ \ + UINT32 r = (WORD); \ + DSB; \ + r = (((r) >> (BIT_OFFSET)) & (BIT_MASK)); \ + r; \ + }) + +/** Millisec timeout macros */ +#define RESET_TIME_OUT_MS 10U +#define REG_WRITE_TIME_OUT_MS 50U +#define PHY_RESET_TIME_OUT_MS 100U +#define INIT_FINISH_DELAY 2000U + +struct lan9118_eth_reg_map_t { + uint32_t rx_data_port; /**< Receive FIFO Ports (offset 0x0) */ + uint32_t reserved1[0x7]; + uint32_t tx_data_port; /**< Transmit FIFO Ports (offset 0x20) */ + uint32_t reserved2[0x7]; + + uint32_t rx_status_port; /**< Receive FIFO status port (offset 0x40) */ + uint32_t rx_status_peek; /**< Receive FIFO status peek (offset 0x44) */ + uint32_t tx_status_port; /**< Transmit FIFO status port (offset 0x48) */ + uint32_t tx_status_peek; /**< Transmit FIFO status peek (offset 0x4C) */ + + uint32_t id_revision; /**< Chip ID and Revision (offset 0x50) */ + uint32_t irq_cfg; /**< Main Interrupt Config (offset 0x54) */ + uint32_t irq_status; /**< Interrupt Status (offset 0x58) */ + uint32_t irq_enable; /**< Interrupt Enable Register (offset 0x5C) */ + uint32_t reserved3; /**< Reserved for future use (offset 0x60) */ + uint32_t byte_test; /**< Byte order test 87654321h (offset 0x64) */ + uint32_t fifo_level_irq; /**< FIFO Level Interrupts (offset 0x68) */ + uint32_t rx_cfg; /**< Receive Configuration (offset 0x6C) */ + uint32_t tx_cfg; /**< Transmit Configuration (offset 0x70) */ + uint32_t hw_cfg; /**< Hardware Configuration (offset 0x74) */ + uint32_t rx_datapath_ctrl; /**< RX Datapath Control (offset 0x78) */ + uint32_t rx_fifo_inf; /**< Receive FIFO Information (offset 0x7C) */ + uint32_t tx_fifo_inf; /**< Transmit FIFO Information (offset 0x80) */ + uint32_t pmt_ctrl; /**< Power Management Control (offset 0x84) */ + uint32_t gpio_cfg; /**< GPIO Configuration (offset 0x88) */ + uint32_t gptimer_cfg; /**< GP Timer Configuration (offset 0x8C) */ + uint32_t gptimer_count; /**< GP Timer Count (offset 0x90) */ + uint32_t reserved4; /**< Reserved for future use (offset 0x94) */ + uint32_t word_swap; /**< WORD SWAP Register (offset 0x98) */ + uint32_t free_run_counter; /**< Free Run Counter (offset 0x9C) */ + uint32_t rx_dropped_frames; /**< RX Dropped Frames Counter (offset 0xA0) */ + uint32_t mac_csr_cmd; /**< MAC CSR Synchronizer Cmd (offset 0xA4) */ + uint32_t mac_csr_data; /**< MAC CSR Synchronizer Data (offset 0xA8) */ + uint32_t afc_cfg; /**< AutomaticFlow Ctrl Config (offset 0xAC) */ + uint32_t eeprom_cmd; /**< EEPROM Command (offset 0xB0) */ + uint32_t eeprom_data; /**< EEPROM Data (offset 0xB4) */ +}; + +/** + * \brief FIFO Info definitions + * + */ +#define FIFO_USED_SPACE_MASK 0xFFFFU +#define DATA_FIFO_USED_SPACE_POS 0U + +/** + * \brief MAC CSR Synchronizer Command bit definitions + * + */ +enum mac_csr_cmd_bits_t { + MAC_CSR_CMD_RW_INDEX = 30U, + MAC_CSR_CMD_BUSY_INDEX = 31U, +}; + +#define MAC_CSR_CMD_ADDRESS_MASK 0x0FU + +/** + * \brief MAC Control register bit definitions + * + */ +enum mac_reg_cr_bits_t { MAC_REG_CR_RXEN_INDEX = 2U, MAC_REG_CR_TXEN_INDEX = 3U }; + +/** + * \brief MII Access register bit definitions + * + */ +enum mac_reg_mii_acc_bits_t { + MAC_REG_MII_ACC_BUSY_INDEX = 0U, + MAC_REG_MII_ACC_WRITE_INDEX = 1U, + MAC_REG_MII_ACC_PHYADDR_INDEX = 11U +}; +#define MAC_REG_MII_ACC_MII_REG_MASK 0x1FU +#define MAC_REG_MII_ACC_MII_REG_OFFSET 6U + +/** + * \brief Hardware config register bit definitions + * + */ +enum hw_cfg_reg_bits_t { + HW_CFG_REG_SRST_INDEX = 0U, + HW_CFG_REG_SRST_TIMEOUT_INDEX = 1U, + HW_CFG_REG_MUST_BE_ONE_INDEX = 20U, +}; +#define HW_CFG_REG_TX_FIFO_SIZE_POS 16U +#define HW_CFG_REG_TX_FIFO_SIZE_MIN 2U /*< Min Tx fifo size in KB */ +#define HW_CFG_REG_TX_FIFO_SIZE_MAX 14U /*< Max Tx fifo size in KB */ +#define HW_CFG_REG_TX_FIFO_SIZE 5U /*< Tx fifo size in KB */ + +/** + * \brief EEPROM command register bit definitions + * + */ +enum eeprom_cmd_reg_bits_t { + EEPROM_CMD_REG_BUSY_INDEX = 31U, +}; + +/** + * \brief PHY Basic Control register bit definitions + * + */ +enum phy_reg_bctrl_reg_bits_t { + PHY_REG_BCTRL_RST_AUTO_NEG_INDEX = 9U, + PHY_REG_BCTRL_AUTO_NEG_EN_INDEX = 12U, + PHY_REG_BCTRL_RESET_INDEX = 15U +}; + +/** + * \brief TX Command A bit definitions + * + */ +#define TX_CMD_DATA_START_OFFSET_BYTES_POS 16U +#define TX_CMD_DATA_START_OFFSET_BYTES_MASK 0x1FU + +enum tx_command_a_bits_t { TX_COMMAND_A_LAST_SEGMENT_INDEX = 12U, TX_COMMAND_A_FIRST_SEGMENT_INDEX = 13U }; + +#define TX_CMD_PKT_LEN_BYTES_MASK 0x7FFU +#define TX_CMD_PKT_TAG_MASK 0xFFFFU +#define TX_CMD_PKT_TAG_POS 16U + +#define RX_FIFO_STATUS_PKT_LENGTH_POS 16U +#define RX_FIFO_STATUS_PKT_LENGTH_MASK 0x3FFFU + +/** + * \brief Interrupt Configuration register bit definitions + * + */ +enum irq_cfg_bits_t { IRQ_CFG_IRQ_EN_INDEX = 8U }; + +#define AFC_BACK_DUR_MASK 0x0FU +#define AFC_BACK_DUR_POS 4U +#define AFC_BACK_DUR 4U /**< equal to 50us */ + +#define AFC_LOW_LEVEL_MASK 0xFFU +#define AFC_LOW_LEVEL_POS 8U +#define AFC_LOW_LEVEL 55U /**< specifies in multiple of 64 bytes */ + +#define AFC_HIGH_LEVEL_MASK 0xFFU +#define AFC_HIGH_LEVEL_POS 16U +#define AFC_HIGH_LEVEL 110U /**< specifies in multiple of 64 bytes */ + +#define BYTE_LEN 4 +/** + * \brief Auto-Negotiation Advertisement register bit definitions + * + */ +enum aneg_bits_t { + ANEG_10_BASE_T_INDEX = 5U, /**< 10Mbps able */ + ANEG_10_BASE_T_FULL_DUPL_INDEX = 6U, /**< 10Mbps with full duplex */ + ANEG_100_BASE_TX_INDEX = 7U, /**< 100Mbps Tx able */ + ANEG_100_BASE_TX_FULL_DUPL_INDEX = 8U, /**< 100Mbps with full duplex */ + ANEG_SYMM_PAUSE_INDEX = 10U, /**< Symmetric Pause */ + ANEG_ASYMM_PAUSE_INDEX = 11U /**< Asymmetric Pause */ +}; + +/** + * \brief Transmit Configuration register bit definitions + * + */ +enum tx_cfg_bits_t { + TX_CFG_STOP_INDEX = 0U, /*< stop */ + TX_CFG_ON_INDEX = 1U, /*< on */ + TX_CFG_AO_INDEX = 2U, /*< allow overrun */ + TX_CFG_TXD_DUMP_INDEX = 14U, /*< Data FIFO dump */ + TX_CFG_TXS_DUMP_INDEX = 15U /*< Status FIFO dump */ +}; + +/** + * \brief Chip ID definitions + * + */ +#define CHIP_ID 0x1180001 + +/** + * Helper struct to hold private data used to operate your ethernet interface. + * Keeping the ethernet address of the MAC in this struct is not necessary + * as it is already kept in the struct netif. + */ +struct EtherNetif { + struct eth_addr* ethaddr; +}; + +static void DelayMs(uint32_t ms) +{ + uint32_t delayMs = 1000; + delayMs = delayMs * ms; + usleep(delayMs); +} + +static void* GetPayloadAddr(const struct pbuf* buf) +{ + return buf->payload; +} + +static void SetTotalLen(struct pbuf* pbuf) +{ + if (!pbuf->next) { + pbuf->tot_len = pbuf->len; + return; + } + + uint32_t total_len; + struct pbuf* pbuf_tailing; + + while (pbuf) { + total_len = pbuf->len; + + pbuf_tailing = pbuf->next; + while (pbuf_tailing) { + total_len += pbuf_tailing->len; + pbuf_tailing = pbuf_tailing->next; + } + + pbuf->tot_len = total_len; + pbuf = pbuf->next; + } +} + +static void AlignMemory(struct pbuf* pbuf, uint32_t const align) +{ + if (!align) { + return; + } + + struct pbuf* pbuf_start = pbuf; + + while (pbuf) { + uint32_t remainder = ((uint32_t)pbuf->payload) % align; + if (remainder) { + uint32_t offset = align - remainder; + if (offset >= align) { + offset = align; + } + pbuf->payload = ((char*)pbuf->payload) + offset; + } + pbuf->len -= align; + pbuf = pbuf->next; + } + + // Correct total lengths + SetTotalLen(pbuf_start); +} + +static struct pbuf* AllocHeap(const uint32_t size, uint32_t const align) +{ + struct pbuf* pbuf = pbuf_alloc(PBUF_RAW, size + align, PBUF_RAM); + if (pbuf == NULL) { + return NULL; + } + + AlignMemory(pbuf, align); + + return pbuf; +} + +static void SetLen(const struct pbuf* buf, const uint32_t len) +{ + struct pbuf* pbuf = buf; + pbuf->len = len; + SetTotalLen(pbuf); +} + +static uint32_t GetLen(const struct pbuf* buf) +{ + return buf->len; +} + +static uint32_t GetTotalLen(const struct pbuf* buf) +{ + return buf->tot_len; +} + +static void fill_tx_fifo(const struct lan9118_eth_dev_t* dev, uint8_t* data, uint32_t size_bytes) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + uint32_t tx_data_port_tmp = 0; + uint8_t* tx_data_port_tmp_ptr = (uint8_t*)&tx_data_port_tmp; + +#ifdef ETH_PAD_SIZE + data += ETH_PAD_SIZE; +#endif + + uint32_t remainder_bytes = (size_bytes % 4); + + if (remainder_bytes > 0) { + uint32_t filler_bytes = (4 - remainder_bytes); + + for (uint32_t i = 0; i < 4; i++) { + if (i < filler_bytes) { + tx_data_port_tmp_ptr[i] = 0; + } else { + tx_data_port_tmp_ptr[i] = data[i - filler_bytes]; + } + } + + SET_BIT_FIELD(register_map->tx_data_port, 0xFFFFFFFF, 0, tx_data_port_tmp); + + size_bytes -= remainder_bytes; + data += remainder_bytes; + } + + while (size_bytes > 0) { + /* Keep the same endianness in data as in the temp variable */ + tx_data_port_tmp_ptr[0] = data[0]; + tx_data_port_tmp_ptr[1] = data[1]; + tx_data_port_tmp_ptr[2] = data[2]; + tx_data_port_tmp_ptr[3] = data[3]; + + SET_BIT_FIELD(register_map->tx_data_port, 0xFFFFFFFF, 0, tx_data_port_tmp); + + data += BYTE_LEN; + size_bytes -= BYTE_LEN; + } +} + +static void empty_rx_fifo(const struct lan9118_eth_dev_t* dev, uint8_t* data, uint32_t size_bytes) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + uint32_t rx_data_port_tmp = 0; + uint8_t* rx_data_port_tmp_ptr = (uint8_t*)&rx_data_port_tmp; + +#ifdef ETH_PAD_SIZE + data += ETH_PAD_SIZE; +#endif + + uint32_t remainder_bytes = (size_bytes % 4); + size_bytes -= remainder_bytes; + + while (size_bytes > 0) { + /* Keep the same endianness in data as in the temp variable */ + rx_data_port_tmp = GET_BIT_FIELD(register_map->rx_data_port, 0xFFFFFFFF, 0); + + data[0] = rx_data_port_tmp_ptr[0]; + data[1] = rx_data_port_tmp_ptr[1]; + data[2] = rx_data_port_tmp_ptr[2]; + data[3] = rx_data_port_tmp_ptr[3]; + + data += BYTE_LEN; + size_bytes -= BYTE_LEN; + } + + if (remainder_bytes > 0) { + rx_data_port_tmp = GET_BIT_FIELD(register_map->rx_data_port, 0xFFFFFFFF, 0); + + for (uint32_t i = 0; i < remainder_bytes; i++) { + data[i] = rx_data_port_tmp_ptr[i]; + } + } +} + +enum lan9118_error_t lan9118_mac_regread(const struct lan9118_eth_dev_t* dev, enum lan9118_mac_reg_offsets_t regoffset, + uint32_t* data) +{ + volatile uint32_t val; + uint32_t maccmd = GET_BIT_FIELD(regoffset, MAC_CSR_CMD_ADDRESS_MASK, 0); + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + /* Make sure there's no pending operation */ + if (!(GET_BIT(register_map->mac_csr_cmd, MAC_CSR_CMD_BUSY_INDEX))) { + SET_BIT(maccmd, MAC_CSR_CMD_RW_INDEX); + SET_BIT(maccmd, MAC_CSR_CMD_BUSY_INDEX); + register_map->mac_csr_cmd = maccmd; /* Start operation */ + + do { + val = register_map->byte_test; /* A no-op read. */ + (void)val; + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while (time_out && GET_BIT(register_map->mac_csr_cmd, MAC_CSR_CMD_BUSY_INDEX)); + + if (!time_out) { + return LAN9118_ERROR_TIMEOUT; + } else { + *data = register_map->mac_csr_data; + } + } else { + return LAN9118_ERROR_BUSY; + } + return LAN9118_ERROR_NONE; +} + +enum lan9118_error_t lan9118_mac_regwrite(const struct lan9118_eth_dev_t* dev, enum lan9118_mac_reg_offsets_t regoffset, + uint32_t data) +{ + volatile uint32_t read = 0; + uint32_t maccmd = GET_BIT_FIELD(regoffset, MAC_CSR_CMD_ADDRESS_MASK, 0); + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + /* Make sure there's no pending operation */ + if (!GET_BIT(register_map->mac_csr_cmd, MAC_CSR_CMD_BUSY_INDEX)) { + register_map->mac_csr_data = data; /* Store data. */ + + CLR_BIT(maccmd, MAC_CSR_CMD_RW_INDEX); + SET_BIT(maccmd, MAC_CSR_CMD_BUSY_INDEX); + + register_map->mac_csr_cmd = maccmd; + + do { + read = register_map->byte_test; /* A no-op read. */ + (void)read; + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while (time_out && (register_map->mac_csr_cmd & GET_BIT(register_map->mac_csr_cmd, MAC_CSR_CMD_BUSY_INDEX))); + if (!time_out) { + return LAN9118_ERROR_TIMEOUT; + } + } else { + return LAN9118_ERROR_BUSY; + } + return LAN9118_ERROR_NONE; +} + +enum lan9118_error_t lan9118_phy_regread(const struct lan9118_eth_dev_t* dev, enum phy_reg_offsets_t regoffset, + uint32_t* data) +{ + uint32_t val = 0; + uint32_t phycmd = 0; + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + if (lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_MII_ACC, &val)) { + return LAN9118_ERROR_INTERNAL; + } + + if (!GET_BIT(val, MAC_REG_MII_ACC_BUSY_INDEX)) { + phycmd = 0; + SET_BIT(phycmd, MAC_REG_MII_ACC_PHYADDR_INDEX); + SET_BIT_FIELD(phycmd, MAC_REG_MII_ACC_MII_REG_MASK, MAC_REG_MII_ACC_MII_REG_OFFSET, regoffset); + CLR_BIT(phycmd, MAC_REG_MII_ACC_WRITE_INDEX); + SET_BIT(phycmd, MAC_REG_MII_ACC_BUSY_INDEX); + + if (lan9118_mac_regwrite(dev, LAN9118_MAC_REG_OFFSET_MII_ACC, phycmd)) { + return LAN9118_ERROR_INTERNAL; + } + + val = 0; + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + if (lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_MII_ACC, &val)) { + return LAN9118_ERROR_INTERNAL; + } + } while (time_out && (GET_BIT(val, MAC_REG_MII_ACC_BUSY_INDEX))); + + if (!time_out) { + return LAN9118_ERROR_TIMEOUT; + } else if (lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_MII_DATA, data)) { + return LAN9118_ERROR_INTERNAL; + } + } else { + return LAN9118_ERROR_BUSY; + } + return LAN9118_ERROR_NONE; +} + +enum lan9118_error_t lan9118_phy_regwrite(const struct lan9118_eth_dev_t* dev, enum phy_reg_offsets_t regoffset, + uint32_t data) +{ + uint32_t val = 0; + uint32_t phycmd = 0; + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + if (lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_MII_ACC, &val)) { + return LAN9118_ERROR_INTERNAL; + } + + if (!GET_BIT(val, MAC_REG_MII_ACC_BUSY_INDEX)) { + /* Load the data */ + if (lan9118_mac_regwrite(dev, LAN9118_MAC_REG_OFFSET_MII_DATA, (data & 0xFFFF))) { + return LAN9118_ERROR_INTERNAL; + } + phycmd = 0; + SET_BIT(phycmd, MAC_REG_MII_ACC_PHYADDR_INDEX); + SET_BIT_FIELD(phycmd, MAC_REG_MII_ACC_MII_REG_MASK, MAC_REG_MII_ACC_MII_REG_OFFSET, regoffset); + SET_BIT(phycmd, MAC_REG_MII_ACC_WRITE_INDEX); + SET_BIT(phycmd, MAC_REG_MII_ACC_BUSY_INDEX); + /* Start operation */ + if (lan9118_mac_regwrite(dev, LAN9118_MAC_REG_OFFSET_MII_ACC, phycmd)) { + return LAN9118_ERROR_INTERNAL; + } + + phycmd = 0; + + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + if (lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_MII_ACC, &phycmd)) { + return LAN9118_ERROR_INTERNAL; + } + } while (time_out && GET_BIT(phycmd, 0)); + + if (!time_out) { + return LAN9118_ERROR_TIMEOUT; + } + + } else { + return LAN9118_ERROR_BUSY; + } + return LAN9118_ERROR_NONE; +} + +uint32_t lan9118_read_id(const struct lan9118_eth_dev_t* dev) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + uint32_t lan9118Id = 0; + + lan9118Id = register_map->id_revision; + + return lan9118Id; +} + +enum lan9118_error_t lan9118_soft_reset(const struct lan9118_eth_dev_t* dev) +{ + uint32_t time_out = RESET_TIME_OUT_MS; + + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + /* Soft reset */ + SET_BIT(register_map->hw_cfg, HW_CFG_REG_SRST_INDEX); + + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while (time_out && GET_BIT(register_map->hw_cfg, HW_CFG_REG_SRST_TIMEOUT_INDEX)); + + if (!time_out) { + return LAN9118_ERROR_TIMEOUT; + } + + return LAN9118_ERROR_NONE; +} + +void lan9118_set_txfifo(const struct lan9118_eth_dev_t* dev, uint32_t val) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + if (val >= HW_CFG_REG_TX_FIFO_SIZE_MIN && val <= HW_CFG_REG_TX_FIFO_SIZE_MAX) { + register_map->hw_cfg = val << HW_CFG_REG_TX_FIFO_SIZE_POS; + } +} + +enum lan9118_error_t lan9118_set_fifo_level_irq(const struct lan9118_eth_dev_t* dev, + enum lan9118_fifo_level_irq_pos_t irq_level_pos, uint32_t level) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + if (level < LAN9118_FIFO_LEVEL_IRQ_LEVEL_MIN || level > LAN9118_FIFO_LEVEL_IRQ_LEVEL_MAX) { + return LAN9118_ERROR_PARAM; + } + + CLR_BIT_FIELD(register_map->fifo_level_irq, LAN9118_FIFO_LEVEL_IRQ_MASK, irq_level_pos, + LAN9118_FIFO_LEVEL_IRQ_MASK); + SET_BIT_FIELD(register_map->fifo_level_irq, LAN9118_FIFO_LEVEL_IRQ_MASK, irq_level_pos, level); + return LAN9118_ERROR_NONE; +} + +enum lan9118_error_t lan9118_wait_eeprom(const struct lan9118_eth_dev_t* dev) +{ + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while (time_out && GET_BIT(register_map->eeprom_cmd, EEPROM_CMD_REG_BUSY_INDEX)); + + if (!time_out) { + return LAN9118_ERROR_TIMEOUT; + } + + return LAN9118_ERROR_NONE; +} + +void lan9118_init_irqs(const struct lan9118_eth_dev_t* dev) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + lan9118_disable_all_interrupts(dev); + lan9118_clear_all_interrupts(dev); + + /* Set IRQ deassertion interval */ + SET_BIT_FIELD(register_map->irq_cfg, 0xFFFFFFFF, 0, 0x11); + + /* enable interrupts */ + SET_BIT(register_map->irq_cfg, IRQ_CFG_IRQ_EN_INDEX); +} + +enum lan9118_error_t lan9118_check_phy(const struct lan9118_eth_dev_t* dev) +{ + uint32_t phyid1 = 0; + uint32_t phyid2 = 0; + + if (lan9118_phy_regread(dev, LAN9118_PHY_REG_OFFSET_ID1, &phyid1)) { + return LAN9118_ERROR_INTERNAL; + } + if (lan9118_phy_regread(dev, LAN9118_PHY_REG_OFFSET_ID2, &phyid2)) { + return LAN9118_ERROR_INTERNAL; + } + if ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || (phyid1 == 0x0 && phyid2 == 0x0)) { + return LAN9118_ERROR_INTERNAL; + } + return LAN9118_ERROR_NONE; +} + +enum lan9118_error_t lan9118_reset_phy(const struct lan9118_eth_dev_t* dev) +{ + uint32_t read = 0; + + if (lan9118_phy_regread(dev, LAN9118_PHY_REG_OFFSET_BCTRL, &read)) { + return LAN9118_ERROR_INTERNAL; + } + + SET_BIT(read, PHY_REG_BCTRL_RESET_INDEX); + if (lan9118_phy_regwrite(dev, LAN9118_PHY_REG_OFFSET_BCTRL, read)) { + return LAN9118_ERROR_INTERNAL; + } + + return LAN9118_ERROR_NONE; +} + +void lan9118_advertise_cap(const struct lan9118_eth_dev_t* dev) +{ + uint32_t aneg_adv = 0; + lan9118_phy_regread(dev, LAN9118_PHY_REG_OFFSET_ANEG_ADV, &aneg_adv); + + SET_BIT(aneg_adv, ANEG_10_BASE_T_INDEX); + SET_BIT(aneg_adv, ANEG_10_BASE_T_FULL_DUPL_INDEX); + SET_BIT(aneg_adv, ANEG_100_BASE_TX_INDEX); + SET_BIT(aneg_adv, ANEG_100_BASE_TX_FULL_DUPL_INDEX); + SET_BIT(aneg_adv, ANEG_SYMM_PAUSE_INDEX); + SET_BIT(aneg_adv, ANEG_ASYMM_PAUSE_INDEX); + + lan9118_phy_regwrite(dev, LAN9118_PHY_REG_OFFSET_ANEG_ADV, aneg_adv); +} + +void lan9118_enable_xmit(const struct lan9118_eth_dev_t* dev) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + SET_BIT(register_map->tx_cfg, TX_CFG_ON_INDEX); +} + +void lan9118_enable_mac_xmit(const struct lan9118_eth_dev_t* dev) +{ + uint32_t mac_cr = 0; + lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_CR, &mac_cr); + + SET_BIT(mac_cr, MAC_REG_CR_TXEN_INDEX); + + lan9118_mac_regwrite(dev, LAN9118_MAC_REG_OFFSET_CR, mac_cr); +} + +void lan9118_enable_mac_recv(const struct lan9118_eth_dev_t* dev) +{ + uint32_t mac_cr = 0; + lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_CR, &mac_cr); + + SET_BIT(mac_cr, MAC_REG_CR_RXEN_INDEX); + + lan9118_mac_regwrite(dev, LAN9118_MAC_REG_OFFSET_CR, mac_cr); +} + +int lan9118_check_id(const struct lan9118_eth_dev_t* dev) +{ + uint32_t id = lan9118_read_id(dev); + + return ((id == CHIP_ID) ? 0 : 1); +} + +void lan9118_enable_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + SET_BIT(register_map->irq_enable, source); +} + +void lan9118_disable_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + CLR_BIT(register_map->irq_enable, source); +} + +void lan9118_disable_all_interrupts(const struct lan9118_eth_dev_t* dev) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + register_map->irq_enable = 0; +} + +void lan9118_clear_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + SET_BIT(register_map->irq_status, source); +} + +void lan9118_clear_all_interrupts(const struct lan9118_eth_dev_t* dev) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + register_map->irq_status = UINT32_MAX; +} + +int lan9118_get_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + return GET_BIT(register_map->irq_status, source); +} + +void lan9118_establish_link(const struct lan9118_eth_dev_t* dev) +{ + uint32_t bcr = 0; + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + lan9118_phy_regread(dev, LAN9118_PHY_REG_OFFSET_BCTRL, &bcr); + SET_BIT(bcr, PHY_REG_BCTRL_AUTO_NEG_EN_INDEX); + SET_BIT(bcr, PHY_REG_BCTRL_RST_AUTO_NEG_INDEX); + lan9118_phy_regwrite(dev, LAN9118_PHY_REG_OFFSET_BCTRL, bcr); + + SET_BIT(register_map->hw_cfg, HW_CFG_REG_MUST_BE_ONE_INDEX); +} + +enum lan9118_error_t lan9118_read_mac_address(const struct lan9118_eth_dev_t* dev, char* mac) +{ + uint32_t mac_low = 0; + uint32_t mac_high = 0; + + if (!mac) { + return LAN9118_ERROR_PARAM; + } + + if (lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_ADDRH, &mac_high)) { + return LAN9118_ERROR_INTERNAL; + } + if (lan9118_mac_regread(dev, LAN9118_MAC_REG_OFFSET_ADDRL, &mac_low)) { + return LAN9118_ERROR_INTERNAL; + } + mac[0] = mac_low & 0xFF; + mac[1] = (mac_low >> 8) & 0xFF; + mac[2] = (mac_low >> 16) & 0xFF; + mac[3] = (mac_low >> 24) & 0xFF; + mac[4] = mac_high & 0xFF; + mac[5] = (mac_high >> 8) & 0xFF; + + return LAN9118_ERROR_NONE; +} + +enum lan9118_error_t lan9118_init(const struct lan9118_eth_dev_t* dev, void (*wait_ms_function)(uint32_t)) +{ + uint32_t phyreset = 0; + enum lan9118_error_t error = LAN9118_ERROR_NONE; + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + if (!wait_ms_function) { + return LAN9118_ERROR_PARAM; + } + dev->data->wait_ms = wait_ms_function; + + error = lan9118_check_id(dev); + if (error != LAN9118_ERROR_NONE) { + return error; + } + + error = lan9118_soft_reset(dev); + if (error != LAN9118_ERROR_NONE) { + return error; + } + + lan9118_set_txfifo(dev, HW_CFG_REG_TX_FIFO_SIZE); + + SET_BIT_FIELD(register_map->afc_cfg, AFC_BACK_DUR_MASK, AFC_BACK_DUR_POS, AFC_BACK_DUR); + SET_BIT_FIELD(register_map->afc_cfg, AFC_LOW_LEVEL_MASK, AFC_LOW_LEVEL_POS, AFC_LOW_LEVEL); + SET_BIT_FIELD(register_map->afc_cfg, AFC_HIGH_LEVEL_MASK, AFC_HIGH_LEVEL_POS, AFC_HIGH_LEVEL); + + error = lan9118_wait_eeprom(dev); + if (error != LAN9118_ERROR_NONE) { + return error; + } + + lan9118_init_irqs(dev); + + /* Configure MAC addresses here if needed. */ + error = lan9118_check_phy(dev); + if (error != LAN9118_ERROR_NONE) { + return error; + } + + error = lan9118_reset_phy(dev); + if (error != LAN9118_ERROR_NONE) { + return error; + } + + if (dev->data->wait_ms) { + dev->data->wait_ms(PHY_RESET_TIME_OUT_MS); + } + /* Checking whether phy reset completed successfully.*/ + error = lan9118_phy_regread(dev, LAN9118_PHY_REG_OFFSET_BCTRL, &phyreset); + if (error != LAN9118_ERROR_NONE) { + return error; + } + + if (GET_BIT(phyreset, PHY_REG_BCTRL_RESET_INDEX)) { + return LAN9118_ERROR_INTERNAL; + } + + lan9118_advertise_cap(dev); + lan9118_establish_link(dev); + lan9118_enable_mac_xmit(dev); + lan9118_enable_xmit(dev); + lan9118_enable_mac_recv(dev); + + /* This sleep is compulsory otherwise txmit/receive will fail. */ + if (dev->data->wait_ms) { + dev->data->wait_ms(INIT_FINISH_DELAY); + } + dev->data->state = 1; + + return LAN9118_ERROR_NONE; +} + +enum lan9118_error_t lan9118_send_by_chunks(const struct lan9118_eth_dev_t* dev, uint32_t total_payload_length, + bool is_new_packet, const char* data, uint32_t current_size) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + bool is_first_segment = false; + bool is_last_segment = false; + uint32_t txcmd_a, txcmd_b = 0; + uint32_t tx_buffer_free_space = 0; + volatile uint32_t xmit_stat = 0; + + if (!data) { + return LAN9118_ERROR_PARAM; + } + + if (is_new_packet) { + is_first_segment = true; + dev->data->ongoing_packet_length = total_payload_length; + dev->data->ongoing_packet_length_sent = 0; + } else if (dev->data->ongoing_packet_length != total_payload_length || + dev->data->ongoing_packet_length_sent >= total_payload_length) { + return LAN9118_ERROR_PARAM; + } + + /* Would next chunk fit into buffer? */ + tx_buffer_free_space = GET_BIT_FIELD(register_map->tx_fifo_inf, FIFO_USED_SPACE_MASK, DATA_FIFO_USED_SPACE_POS); + + if (current_size > tx_buffer_free_space) { + return LAN9118_ERROR_INTERNAL; /* Not enough space in FIFO */ + } + if ((dev->data->ongoing_packet_length_sent + current_size) == total_payload_length) { + is_last_segment = true; + } + + txcmd_a = 0; + txcmd_b = 0; + + if (is_last_segment) { + SET_BIT(txcmd_a, TX_COMMAND_A_LAST_SEGMENT_INDEX); + } + if (is_first_segment) { + SET_BIT(txcmd_a, TX_COMMAND_A_FIRST_SEGMENT_INDEX); + } + + uint32_t data_start_offset_bytes = (4 - (current_size % 4)); + + SET_BIT_FIELD(txcmd_a, TX_CMD_PKT_LEN_BYTES_MASK, 0, current_size); + SET_BIT_FIELD(txcmd_a, TX_CMD_DATA_START_OFFSET_BYTES_MASK, TX_CMD_DATA_START_OFFSET_BYTES_POS, + data_start_offset_bytes); + + SET_BIT_FIELD(txcmd_b, TX_CMD_PKT_LEN_BYTES_MASK, 0, current_size); + SET_BIT_FIELD(txcmd_b, TX_CMD_PKT_TAG_MASK, TX_CMD_PKT_TAG_POS, current_size); + + SET_BIT_FIELD(register_map->tx_data_port, 0xFFFFFFFF, 0, txcmd_a); + SET_BIT_FIELD(register_map->tx_data_port, 0xFFFFFFFF, 0, txcmd_b); + + fill_tx_fifo(dev, (uint8_t*)data, current_size); + + if (is_last_segment) { + /* Pop status port for error check */ + xmit_stat = register_map->tx_status_port; + (void)xmit_stat; + } + dev->data->ongoing_packet_length_sent += current_size; + return LAN9118_ERROR_NONE; +} + +uint32_t lan9118_get_rxfifo_data_used_space(const struct lan9118_eth_dev_t* dev) +{ + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + return GET_BIT_FIELD(register_map->rx_fifo_inf, FIFO_USED_SPACE_MASK, DATA_FIFO_USED_SPACE_POS); +} + +uint32_t lan9118_receive_by_chunks(const struct lan9118_eth_dev_t* dev, char* data, uint32_t dlen) +{ + uint32_t rxfifo_inf = 0; + uint32_t rxfifo_stat = 0; + uint32_t packet_length_byte = 0; + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + if (!data) { + return 0; /* Invalid input parameter, cannot read */ + } + + rxfifo_inf = GET_BIT_FIELD(register_map->rx_fifo_inf, 0xFFFFFFFF, 0); + + if (rxfifo_inf & 0xFFFF) { /* If there's data */ + rxfifo_stat = GET_BIT_FIELD(register_map->rx_status_port, 0xFFFFFFFF, 0); + if (rxfifo_stat != 0) { /* Fetch status of this packet */ + /* Ethernet controller is padding to 32bit aligned data */ + packet_length_byte = + GET_BIT_FIELD(rxfifo_stat, RX_FIFO_STATUS_PKT_LENGTH_MASK, RX_FIFO_STATUS_PKT_LENGTH_POS); + + dev->data->current_rx_size_words = packet_length_byte; + } + } + + empty_rx_fifo(dev, (uint8_t*)data, packet_length_byte); + dev->data->current_rx_size_words = 0; + + return packet_length_byte; +} + +uint32_t lan9118_peek_next_packet_size(const struct lan9118_eth_dev_t* dev) +{ + uint32_t packet_size = 0; + struct lan9118_eth_reg_map_t* register_map = (struct lan9118_eth_reg_map_t*)dev->cfg->base; + + if (lan9118_get_rxfifo_data_used_space(dev)) { + packet_size = + GET_BIT_FIELD(register_map->rx_status_peek, RX_FIFO_STATUS_PKT_LENGTH_MASK, RX_FIFO_STATUS_PKT_LENGTH_POS); + } + return packet_size; +} + +struct pbuf* LowLevelInput(void) +{ + struct pbuf* p = NULL; + uint32_t messageLength = 0; + uint32_t receivedBytes = 0; + + messageLength = lan9118_peek_next_packet_size(g_dev); + if (messageLength == 0) { + return p; + } + + p = AllocHeap(LAN9118_ETH_MAX_FRAME_SIZE, LAN9118_BUFF_ALIGNMENT); + if (p != NULL) { + LOS_TaskLock(); + + receivedBytes = lan9118_receive_by_chunks(g_dev, (char*)GetPayloadAddr(p), GetLen(p)); + if (receivedBytes == 0) { + pbuf_free(p); + p = NULL; + } else { + receivedBytes += 2; + SetLen(p, receivedBytes); + } + + LOS_TaskUnlock(); + } + + return p; +} + +err_t Lan9118LinkOut(struct netif* netif, struct pbuf* buf) +{ + uint32_t bufferLength = 0; + + if (buf == NULL) { + return ERR_BUF; + } else { + bufferLength = GetTotalLen(buf) - ETH_PAD_SIZE; + + LOS_TaskLock(); + + lan9118_send_by_chunks(g_dev, bufferLength, true, (const char*)GetPayloadAddr(buf), bufferLength); + + LOS_TaskUnlock(); + + return ERR_OK; + } +} + +void Lan9118PacketRx(void) +{ + struct pbuf* buf; + + buf = LowLevelInput(); + + if (buf != NULL) { + + LOS_TaskLock(); + if (g_NetIf.input(buf, &g_NetIf) != ERR_OK) { + PRINT_ERR("Emac LWIP: IP input error\n"); + pbuf_free(buf); + } + LOS_TaskUnlock(); + } +} + +void EthernetReceiveHandler(void) +{ + if (lan9118_get_interrupt(g_dev, LAN9118_INTERRUPT_RX_STATUS_FIFO_LEVEL)) { + lan9118_clear_interrupt(g_dev, LAN9118_INTERRUPT_RX_STATUS_FIFO_LEVEL); + + lan9118_disable_interrupt(g_dev, LAN9118_INTERRUPT_RX_STATUS_FIFO_LEVEL); + + Lan9118PacketRx(); + + lan9118_enable_interrupt(g_dev, LAN9118_INTERRUPT_RX_STATUS_FIFO_LEVEL); + } + + return; +} + +void LowLevelInit(struct netif* netif) +{ + enum lan9118_error_t ret = LAN9118_ERROR_NONE; + + /* set MAC hardware address length */ + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* maximum transfer unit */ + netif->mtu = LAN9118_ETH_MTU_SIZE; + + /* set MAC hardware address */ + ret = lan9118_read_mac_address(g_dev, (char*)netif->hwaddr); + if (ret != LAN9118_ERROR_NONE) { + PRINT_ERR("get mac addr error\n"); + return; + } + + /* Interface capabilities */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_LINK_UP; + +#if LWIP_IPV6 && LWIP_IPV6_MLD + /* + * For hardware/netifs that implement MAC filtering. + * All-nodes link-local is handled by default, so we must let the hardware + * know to allow multicast packets in. Should set mld_mac_filter previously. + */ + if (netif->mld_mac_filter != NULL) { + ip6_addr_t ip6_allnodes_ll; + ip6_addr_set_allnodes_linklocal(&ip6_allnodes_ll); + netif->mld_mac_filter(netif, &ip6_allnodes_ll, NETIF_ADD_MAC_FILTER); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ +} + +err_t EthernetifInit(struct netif* netif) +{ + struct EtherNetif* ethernetif; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + ethernetif = mem_malloc(sizeof(struct EtherNetif)); + if (ethernetif == NULL) { + PRINT_ERR("EthernetifInit: out of memory\n"); + return ERR_MEM; + } + + netif->state = ethernetif; + netif->link_layer_type = ETHERNET_DRIVER_IF; + +#if LWIP_NETIF_HOSTNAME + netif->hostname = LAN9118_NETIF_NAME; +#endif + + memcpy(netif->name, LAN9118_NETIF_NICK, (sizeof(netif->name) < sizeof(LAN9118_NETIF_NICK)) ? sizeof(netif->name) : sizeof(LAN9118_NETIF_NICK)); + memcpy(netif->full_name, LAN9118_NETIF_NICK, (IFNAMSIZ < sizeof(LAN9118_NETIF_NICK)) ? IFNAMSIZ : sizeof(LAN9118_NETIF_NICK)); + + /* Initialize the hardware */ + enum lan9118_error_t init_successful = lan9118_init(g_dev, &DelayMs); + if (init_successful != LAN9118_ERROR_NONE) { + return false; + } + + /* Init FIFO level interrupts: use Rx status level irq to trigger + * interrupts for any non-processed packets, while Tx is not irq driven */ + lan9118_set_fifo_level_irq(g_dev, LAN9118_FIFO_LEVEL_IRQ_RX_STATUS_POS, LAN9118_FIFO_LEVEL_IRQ_LEVEL_MIN); + lan9118_set_fifo_level_irq(g_dev, LAN9118_FIFO_LEVEL_IRQ_TX_STATUS_POS, LAN9118_FIFO_LEVEL_IRQ_LEVEL_MIN); + lan9118_set_fifo_level_irq(g_dev, LAN9118_FIFO_LEVEL_IRQ_TX_DATA_POS, LAN9118_FIFO_LEVEL_IRQ_LEVEL_MAX); + + /* Enable Ethernet interrupts */ + lan9118_enable_interrupt(g_dev, LAN9118_INTERRUPT_RX_STATUS_FIFO_LEVEL); + (void)LOS_HwiCreate(ETHERNET_IRQn, 0, 0, (HWI_PROC_FUNC)EthernetReceiveHandler, 0); + +#if LWIP_IPV4 + netif->output = etharp_output; +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 + netif->output_ip6 = ethip6_output; +#endif /* LWIP_IPV6 */ + + netif->linkoutput = Lan9118LinkOut; + + /* initialize mac */ + LowLevelInit(netif); + + return ERR_OK; +} + +void Lan9118NetInit(void) +{ + ip4_addr_t ip; + ip4_addr_t mask; + ip4_addr_t gw; + static uint32_t overtime = 0; + struct netif* NetifInitRet; + + ip.addr = ipaddr_addr(LAN9118_NETIF_TEST_IP); + mask.addr = ipaddr_addr(LAN9118_NETIF_TEST_MASK); + gw.addr = ipaddr_addr(LAN9118_NETIF_TEST_GW); + + NetifInitRet = netif_add(&g_NetIf, &ip, &mask, &gw, g_NetIf.state, EthernetifInit, tcpip_input); + if (NetifInitRet == NULL) { + PRINT_ERR("NetifInit error!\n"); + return; + } + + netif_set_default(&g_NetIf); + netifapi_netif_set_up(&g_NetIf); + do { + DelayMs(SLEEP_TIME_MS); + overtime++; + if (overtime > NETIF_SETUP_OVERTIME) { + PRINT_ERR("netif_is_link_up overtime!\n"); + break; + } + } while (netif_is_link_up(&g_NetIf) == 0); + if (overtime <= NETIF_SETUP_OVERTIME) { + printf("netif init succeed!\n"); + } +} + +void NetInit(void) +{ + + printf("tcpip_init start\n"); + + tcpip_init(NULL, NULL); + + printf("tcpip_init end\n"); + + Lan9118NetInit(); +} diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/net/lan9118_eth_drv.h b/arm_mps2_an386_clang/liteos_m/board/driver/net/lan9118_eth_drv.h new file mode 100644 index 0000000000000000000000000000000000000000..fc8e665a32c1695a585cee0c18f2a3f076e70a9e --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/net/lan9118_eth_drv.h @@ -0,0 +1,546 @@ +/* + * Copyright (c) 2016-2019 Arm Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file lan9118_drv.h + * \brief Generic driver for LAN9118 Ethernet controller + */ + +#ifndef __LAN9118_ETH_H__ +#define __LAN9118_ETH_H__ + +#include +#include +#include "los_config.h" +#include "los_event.h" +#include "los_interrupt.h" +#include "los_reg.h" +#include "stdio.h" +#include "los_reg.h" +#include "los_arch_context.h" +#include "netinet/if_ether.h" +#include "lwip/opt.h" +#include +#include "lwip/etharp.h" +#include "lwip/tcpip.h" +#include "lwip/mem.h" +#include +#include + +#define LAN9118_BASE 0x40200000UL /* Ethernet LAN9118 BASE Address */ +#define ETHERNET_IRQn 13 /* Ethernet Interrupt */ +#define LAN9118_ETH_MTU_SIZE 1500U /* Ethernet MTU */ + +/** LAN9118 device configuration structure */ +struct lan9118_eth_dev_cfg_t { + const uint32_t base; /*!< LAN9118 base address */ +}; + +/** LAN9118 device data structure */ +struct lan9118_eth_dev_data_t { + uint32_t state; /*!< Indicates if the LAN9118 driver + is initialized and enabled */ + void (*wait_ms)(uint32_t); /*!< function pointer to system's millisec delay + function, will be used for delays */ + uint32_t ongoing_packet_length; /*!< size in bytes of the packet + is being sent */ + uint32_t ongoing_packet_length_sent; /*!< size in bytes of the packet + has been sent */ + uint32_t current_rx_size_words; /*!< Data length in words, + currently is being read */ +}; + +/** LAN9118 device structure */ +struct lan9118_eth_dev_t { + const struct lan9118_eth_dev_cfg_t* const cfg; /*!< configuration */ + struct lan9118_eth_dev_data_t* const data; /*!< data */ +}; + +/** + * \brief Error code definitions + * + */ +enum lan9118_error_t { + LAN9118_ERROR_NONE = 0U, /*!< no error */ + LAN9118_ERROR_TIMEOUT = 1U, /*!< timeout */ + LAN9118_ERROR_BUSY = 2U, /*!< no error */ + LAN9118_ERROR_PARAM = 3U, /*!< invalid parameter */ + LAN9118_ERROR_INTERNAL = 4U /*!< internal error */ +}; + +/** + * \brief Interrupt source definitions + * + */ +enum lan9118_interrupt_source { + LAN9118_INTERRUPT_GPIO0 = 0U, + LAN9118_INTERRUPT_GPIO1 = 1U, + LAN9118_INTERRUPT_GPIO2 = 2U, + LAN9118_INTERRUPT_RX_STATUS_FIFO_LEVEL = 3U, + LAN9118_INTERRUPT_RX_STATUS_FIFO_FULL = 4U, + /* 5 Reserved according to Datasheet */ + LAN9118_INTERRUPT_RX_DROPPED_FRAME = 6U, + LAN9118_INTERRUPT_TX_STATUS_FIFO_LEVEL = 7U, + LAN9118_INTERRUPT_TX_STATUS_FIFO_FULL = 8U, + LAN9118_INTERRUPT_TX_DATA_FIFO_AVAILABLE = 9U, + LAN9118_INTERRUPT_TX_DATA_FIFO_OVERRUN = 10U, + /* 11, 12 Reserved according to Datasheet */ + LAN9118_INTERRUPT_TX_ERROR = 13U, + LAN9118_INTERRUPT_RX_ERROR = 14U, + LAN9118_INTERRUPT_RX_WATCHDOG_TIMEOUT = 15U, + LAN9118_INTERRUPT_TX_STATUS_OVERFLOW = 16U, + LAN9118_INTERRUPT_TX_POWER_MANAGEMENT = 17U, + LAN9118_INTERRUPT_PHY = 18U, + LAN9118_INTERRUPT_GP_TIMER = 19U, + LAN9118_INTERRUPT_RX_DMA = 20U, + LAN9118_INTERRUPT_TX_IOC = 21U, + /* 22 Reserved according to Datasheet*/ + LAN9118_INTERRUPT_RX_DROPPED_FRAME_HALF = 23U, + LAN9118_INTERRUPT_RX_STOPPED = 24U, + LAN9118_INTERRUPT_TX_STOPPED = 25U, + /* 26 - 30 Reserved according to Datasheet*/ + LAN9118_INTERRUPT_SW = 31U +}; + +/** + * \brief MAC register offset definitions + * + */ +enum lan9118_mac_reg_offsets_t { + LAN9118_MAC_REG_OFFSET_CR = 0x1U, + LAN9118_MAC_REG_OFFSET_ADDRH = 0x2U, + LAN9118_MAC_REG_OFFSET_ADDRL = 0x3U, + LAN9118_MAC_REG_OFFSET_HASHH = 0x4U, + LAN9118_MAC_REG_OFFSET_HASHL = 0x5U, + LAN9118_MAC_REG_OFFSET_MII_ACC = 0x6U, + LAN9118_MAC_REG_OFFSET_MII_DATA = 0x7U, + LAN9118_MAC_REG_OFFSET_FLOW = 0x8U, + LAN9118_MAC_REG_OFFSET_VLAN1 = 0x9U, + LAN9118_MAC_REG_OFFSET_VLAN2 = 0xAU, + LAN9118_MAC_REG_OFFSET_WUFF = 0xBU, + LAN9118_MAC_REG_OFFSET_WUCSR = 0xCU, +}; + +/** + * \brief PHY register offset definitions + * + */ +enum phy_reg_offsets_t { + LAN9118_PHY_REG_OFFSET_BCTRL = 0U, + LAN9118_PHY_REG_OFFSET_BSTATUS = 1U, + LAN9118_PHY_REG_OFFSET_ID1 = 2U, + LAN9118_PHY_REG_OFFSET_ID2 = 3U, + LAN9118_PHY_REG_OFFSET_ANEG_ADV = 4U, + LAN9118_PHY_REG_OFFSET_ANEG_LPA = 5U, + LAN9118_PHY_REG_OFFSET_ANEG_EXP = 6U, + LAN9118_PHY_REG_OFFSET_MCONTROL = 17U, + LAN9118_PHY_REG_OFFSET_MSTATUS = 18U, + LAN9118_PHY_REG_OFFSET_CSINDICATE = 27U, + LAN9118_PHY_REG_OFFSET_INTSRC = 29U, + LAN9118_PHY_REG_OFFSET_INTMASK = 30U, + LAN9118_PHY_REG_OFFSET_CS = 31U +}; + +/** + * \brief FIFO Level Interrupt bit definitions + * + */ +enum lan9118_fifo_level_irq_pos_t { + LAN9118_FIFO_LEVEL_IRQ_RX_STATUS_POS = 0U, + LAN9118_FIFO_LEVEL_IRQ_TX_STATUS_POS = 16U, + LAN9118_FIFO_LEVEL_IRQ_TX_DATA_POS = 24U +}; + +/** + * \brief FIFO Level Interrupt limits + * + */ +#define LAN9118_FIFO_LEVEL_IRQ_MASK 0xFFU +#define LAN9118_FIFO_LEVEL_IRQ_LEVEL_MIN 0U +#define LAN9118_FIFO_LEVEL_IRQ_LEVEL_MAX LAN9118_FIFO_LEVEL_IRQ_MASK + +/** + * \brief Initializes LAN9118 Ethernet controller to a known default state: + * - device ID is checked + * - global interrupt is enabled, but all irq sources are disabled + * - all capabilities are advertised + * - 10Mbps able + * - 10Mbps with full duplex + * - 100Mbps Tx able + * - 100Mbps with full duplex + * - Symmetric Pause + * - Asymmetric Pause + * - Establish link enabled + * - Rx enabled + * - Tx enabled + * Init should be called prior to any other process and + * it's the caller's responsibility to follow proper call order. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] wait_ms_function function pointer to a millisec delay function + * for proper timing of some processes + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_init(const struct lan9118_eth_dev_t* dev, void (*wait_ms_function)(uint32_t)); + +/** + * \brief Reads the MAC register. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] regoffset Register offset + * \param[in, out] data Pointer to register will be read + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_mac_regread(const struct lan9118_eth_dev_t* dev, enum lan9118_mac_reg_offsets_t regoffset, + uint32_t* data); + +/** + * \brief Writes the MAC register. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] regoffset Register offset + * \param[in] data Register value to write + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_mac_regwrite(const struct lan9118_eth_dev_t* dev, enum lan9118_mac_reg_offsets_t regoffset, + uint32_t data); + +/** + * \brief Reads the PHY register. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] regoffset Register offset + * \param[out] data Register value is read + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_phy_regread(const struct lan9118_eth_dev_t* dev, enum phy_reg_offsets_t regoffset, \ + uint32_t* data); + +/** + * \brief Writes the PHY register. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] regoffset Register offset + * \param[in] data Register value to write + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_phy_regwrite(const struct lan9118_eth_dev_t* dev, enum phy_reg_offsets_t regoffset, \ + uint32_t data); + +/** + * \brief Reads the Ethernet Controller's ID. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * + * \return ID number + */ +uint32_t lan9118_read_id(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Initiates a soft reset, returns failure or success. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_soft_reset(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Sets the Maximum Transmission Unit by Tx fifo size. + * Note: The MTU will be smaller than 512 bytes, + * which is used by the status. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] val Size of the fifo in kbytes + * \ref HW_CFG_REG_TX_FIFO_SIZE_MIN + * \ref HW_CFG_REG_TX_FIFO_SIZE_MAX + */ +void lan9118_set_txfifo(const struct lan9118_eth_dev_t* dev, uint32_t val); + +/** + * \brief Sets the FIFO level interrupt for a given source. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] irq_level_pos Bit position of the FIFO to set + * \ref lan9118_fifo_level_irq_pos_t + * \param[in] level Level of the FIFO, when the FIFO used space is greater + * than this value, corresponding interrupt will be generated. + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_set_fifo_level_irq(const struct lan9118_eth_dev_t* dev, + enum lan9118_fifo_level_irq_pos_t irq_level_pos, uint32_t level); + +/** + * \brief Waits for EEPROM to be ready to use. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_wait_eeprom(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Initializes irqs by clearing and disabling all interrupt sources + * and enable interrupts. Since all interrupt sources are disabled, + * interrupt won't be triggered, until interrupt sources won't be + * enabled by \ref lan9118_enable_interrupt + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_init_irqs(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Checks PHY ID registers. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_check_phy(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Resets PHY. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_reset_phy(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Advertises all speeds and pauses capabilities. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_advertise_cap(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Enables transmission. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_enable_xmit(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Enables MAC Transmitter. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_enable_mac_xmit(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Enables receiving. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_enable_mac_recv(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Enables the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] source Enum of the interrupt source. + */ +void lan9118_enable_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source); + +/** + * \brief Disables the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] source Enum of the interrupt source. + */ +void lan9118_disable_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source); + +/** + * \brief Disables all interrupt sources. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_disable_all_interrupts(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Clears the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] source Enum of the interrupt source. + */ +void lan9118_clear_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source); + +/** + * \brief Clears all interrupt sources. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_clear_all_interrupts(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Gets the status of the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] source Enum of the interrupt source. + * + * \return non-zero if the given interrupt source is triggered, zero otherwise + */ +int lan9118_get_interrupt(const struct lan9118_eth_dev_t* dev, enum lan9118_interrupt_source source); + +/** + * \brief Establishes link + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + */ +void lan9118_establish_link(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Reads the Ethernet Controller's MAC address from its EEPROM. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in,out] mac array will include the read MAC address in + * 6 bytes hexadecimal format. + * It should be allocated by the caller to 6 bytes. + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_read_mac_address(const struct lan9118_eth_dev_t* dev, char* mac); + +/** + * \brief Check device ID. + * + * \return error code /ref lan9118_error_t + */ +int lan9118_check_id(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Sends data from the given buffer as an Ethernet packet. + * The full packet length must be specified at the beginning + * of a new packet transmission. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in] total_payload_length Length of the ethernet payload. + * Should be equal to the sum of passed buffers within a packet. + * \param[in] is_new_packet Should be set to true if the input buffer has to + * be sent as the start of a new packet or as a full packet. + * \param[in] data Pointer to the data buffer to be sent. + * \param[in] current_size Size of the data in bytes. + * + * \return error code /ref lan9118_error_t + */ +enum lan9118_error_t lan9118_send_by_chunks(const struct lan9118_eth_dev_t* dev, uint32_t total_payload_length, + bool is_new_packet, const char* data, uint32_t current_size); + +/** + * \brief Reads an incoming Ethernet packet into the given buffer. + * Stops reading at packet border. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * \param[in,out] data Pointer to a pre-allocated input buffer. + * Allocating sufficient memory space is the caller's + * responsibility, which is typically done by calling + * \ref lan9118_peek_next_packet_size. + * \param[in] dlen Length of the allocated data in bytes. + * + * \return Number of bytes read from the Rx FIFO into the given buffer. + */ +uint32_t lan9118_receive_by_chunks(const struct lan9118_eth_dev_t* dev, char* data, uint32_t dlen); + +/** + * \brief Get the used space of Rx fifo in bytes. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * + * \return Data received and waiting for read in bytes + */ +uint32_t lan9118_get_rxfifo_data_used_space(const struct lan9118_eth_dev_t* dev); + +/** + * \brief Gets the size of next unread packet in Rx buffer, using the peak + * register, which is not destructive so can be read asynchronously. + * Warning: In case of heavy receiving loads, this register may not + * be in perfect sync. + * + * \param[in] dev Ethernet device structure \ref lan9118_eth_dev_t + * + * \return Size of the next packet in bytes, read from the Rx Peek register. + */ +uint32_t lan9118_peek_next_packet_size(const struct lan9118_eth_dev_t* dev); + +/** \brief Allocates a buf and returns the data from the incoming + * packet. + * + * \return a buf filled with the received packet + * (including MAC header) + */ +struct pbuf* LowLevelInput(void); + +/** + * \brief Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param netif a pre-allocated netif structure + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ +err_t Lan9118LinkOut(struct netif* netif, struct pbuf* buf); + +/** \brief Packet reception task + * + * This task is called when a packet is received. It will + * pass the packet to the Network Stack. + */ +void Lan9118PacketRx(void); + +/** \brief interrupt called + * + * This task is handle rx data. + */ +void EthernetReceiveHandler(void); + +/** + * \brief In this function, the hardware should be initialized. + * Called from EthernetifInit(). + * + * @param netif the already initialized lwip network interface structure + * for this ethernetif + */ +void LowLevelInit(struct netif* netif); + +/** + * \brief Init net config + * + * This task is called when netif_add() + */ +err_t EthernetifInit(struct netif* netif); + +/** + * \brief Init Lan9118 net + * + */ +void Lan9118NetInit(void); + +/** + * \brief Init net + * + */ +void NetInit(void); + +#endif /* __LAN9118_ETH_H__ */ diff --git a/arm_mps2_an386_clang/liteos_m/board/driver/uart.c b/arm_mps2_an386_clang/liteos_m/board/driver/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..31572aa9272cdb9c0920ce46ff07d96a1101a98f --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/driver/uart.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "uart.h" +#include "arm_uart_drv.h" +#include "stdio.h" +#include "los_config.h" +#include "los_reg.h" +#include "los_interrupt.h" +#include "los_event.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +static const struct arm_uart_dev_cfg_t g_uartCfg = {UART0_BASE, 115200}; +static struct arm_uart_dev_data_t g_uartData = {0}; +struct arm_uart_dev_t g_uartDev; + +INT32 UartGetc(VOID) +{ + UINT8 c; + if (arm_uart_read(&g_uartDev, &c) == ARM_UART_ERR_NOT_READY) { + return 0; + } + + return c; +} + +INT32 UartPutc(INT32 c, VOID *file) +{ + return arm_uart_write(&g_uartDev, (UINT8)c); +} + +VOID UartReceiveHandler(VOID) +{ + if (arm_uart_get_interrupt_status(&g_uartDev) == ARM_UART_IRQ_RX) { + (void)LOS_EventWrite(&g_shellInputEvent, 0x1); + (void)arm_uart_clear_interrupt(&g_uartDev, ARM_UART_IRQ_RX); + } + return; +} + +VOID UartInit(VOID) +{ + g_uartDev.cfg = &g_uartCfg; + g_uartDev.data = &g_uartData; + (void)arm_uart_init(&g_uartDev, UART0_CLK_FREQ); + return; +} + +VOID Uart0RxIrqRegister(VOID) +{ + (void)arm_uart_irq_rx_enable(&g_uartDev); + (void)LOS_HwiCreate(Uart0_Rx_IRQn, 0, 0, (HWI_PROC_FUNC)UartReceiveHandler, 0); + return; +} +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ diff --git a/arm_mps2_an386_clang/liteos_m/board/fs/BUILD.gn b/arm_mps2_an386_clang/liteos_m/board/fs/BUILD.gn new file mode 100644 index 0000000000000000000000000000000000000000..c6dde2fc635526367bdef73536bab2d83d82a235 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/fs/BUILD.gn @@ -0,0 +1,47 @@ +# Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +config("fs_adapter_config") { + include_dirs = [ + ".", + "//device/qemu/arm_mps2_an386/liteos_m/board/driver/flash/", + "//third_party/littlefs", + ] +} + +static_library("fs_adapter") { + sources = [ + "ff_gen_drv.c", + "fs_init.c", + ] + + public_configs = [ ":fs_adapter_config" ] + deps = [ "//device/qemu/arm_mps2_an386/liteos_m/board/driver/flash:flash" ] + + include_dirs = [ "kernel/liteos_m/kernel/include" ] +} diff --git a/arm_mps2_an386_clang/liteos_m/board/fs/ff_gen_drv.c b/arm_mps2_an386_clang/liteos_m/board/fs/ff_gen_drv.c new file mode 100644 index 0000000000000000000000000000000000000000..24d257453d739be4dd1044eb28f57a17edbd15ab --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/fs/ff_gen_drv.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if (LOSCFG_SUPPORT_FATFS == 1) +#include "ff_gen_drv.h" +#include "fatfs.h" +DiskDrvTypeDef g_diskDrv = { { 0 }, { 0 }, { 0 }, { 0 } }; +#endif \ No newline at end of file diff --git a/arm_mps2_an386_clang/liteos_m/board/fs/ff_gen_drv.h b/arm_mps2_an386_clang/liteos_m/board/fs/ff_gen_drv.h new file mode 100644 index 0000000000000000000000000000000000000000..f7ef5fc320579059187165bf010bb6092c64e58c --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/fs/ff_gen_drv.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FF_GEN_DRV_H +#define FF_GEN_DRV_H + +#include "stdint.h" +#ifdef LOSCFG_SUPPORT_FATFS +#include "diskio.h" +#endif + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#if (LOSCFG_SUPPORT_FATFS == 1) +typedef struct { + DSTATUS (*disk_initialize)(BYTE); + DSTATUS (*disk_status)(BYTE); + DSTATUS (*disk_read)(BYTE, BYTE *, DWORD, UINT); + DSTATUS (*disk_write)(BYTE, const BYTE *, DWORD, UINT); + DSTATUS (*disk_ioctl)(BYTE, BYTE, void *); +} DiskioDrvTypeDef; + +typedef struct { + uint8_t initialized[FF_VOLUMES]; + const DiskioDrvTypeDef *drv[FF_VOLUMES]; + uint8_t lun[FF_VOLUMES]; + volatile uint8_t nbr; +} DiskDrvTypeDef; + +extern DiskDrvTypeDef g_diskDrv; +#endif +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* FS_CONFIG_H */ diff --git a/arm_mps2_an386_clang/liteos_m/board/fs/fs_config.h b/arm_mps2_an386_clang/liteos_m/board/fs/fs_config.h new file mode 100644 index 0000000000000000000000000000000000000000..6e22c46ee09c99c7489a276a9d887afc941f4be3 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/fs/fs_config.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FS_CONFIG_H +#define FS_CONFIG_H + +#include "los_compiler.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define FF_VOLUME_STRS "system", "inner", "update", "user" +#define FS_MAX_SS 512 + +#define FAT_MAX_OPEN_FILES 50 + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* FS_CONFIG_H */ diff --git a/arm_mps2_an386_clang/liteos_m/board/fs/fs_init.c b/arm_mps2_an386_clang/liteos_m/board/fs/fs_init.c new file mode 100644 index 0000000000000000000000000000000000000000..ecaa8fe13831e1a890feaf0c1ea490ba05ea42c7 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/fs/fs_init.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "los_config.h" +#include "ram_virt_flash.h" +#include "los_fs.h" + +#if (LOSCFG_SUPPORT_LITTLEFS == 1) + +struct fs_cfg { + CHAR *mount_point; + struct PartitionCfg partCfg; +}; + +INT32 LfsLowLevelInit() +{ + INT32 ret; + struct fs_cfg fs[LOSCFG_LFS_MAX_MOUNT_SIZE] = {0}; + HalLogicPartition *halPartitionsInfo = getPartitionInfo(); + + INT32 lengthArray = halPartitionsInfo[FLASH_PARTITION_DATA0].partitionLength; + INT32 addrArray = halPartitionsInfo[FLASH_PARTITION_DATA0].partitionStartAddr; + ret = LOS_DiskPartition("flash0", "littlefs", &lengthArray, &addrArray, 1); + printf("%s: DiskPartition %s\n", __func__, (ret == 0) ? "succeed" : "failed"); + if (ret != 0) { + return -1; + } + + fs[0].mount_point = "/littlefs"; + fs[0].partCfg.partNo = FLASH_PARTITION_DATA0; + fs[0].partCfg.blockSize = 4096; /* 4096, lfs block size */ + fs[0].partCfg.blockCount = 2048; /* 2048, lfs block count */ + fs[0].partCfg.readFunc = virt_flash_read; + fs[0].partCfg.writeFunc = virt_flash_write; + fs[0].partCfg.eraseFunc = virt_flash_erase; + + fs[0].partCfg.readSize = 256; /* 256, lfs read size */ + fs[0].partCfg.writeSize = 256; /* 256, lfs prog size */ + fs[0].partCfg.cacheSize = 256; /* 256, lfs cache size */ + fs[0].partCfg.lookaheadSize = 16; /* 16, lfs lookahead size */ + fs[0].partCfg.blockCycles = 1000; /* 1000, lfs block cycles */ + + ret = LOS_PartitionFormat("flash0", "littlefs", &fs[0].partCfg); + printf("%s: PartitionFormat %s\n", __func__, (ret == 0) ? "succeed" : "failed"); + if (ret != 0) { + return -1; + } + + ret = mount(NULL, fs[0].mount_point, "littlefs", 0, &fs[0].partCfg); + printf("%s: mount fs on '%s' %s\n", __func__, fs[0].mount_point, (ret == 0) ? "succeed" : "failed"); + if (ret != 0) { + return -1; + } + + ret = mkdir(fs[0].mount_point, 0777); /* 0777, set dir permissions */ + printf("%s: mkdir '%s' %s\n", __func__, fs[0].mount_point, (ret == 0) ? "succeed" : "failed"); + if (ret != 0) { + return -1; + } + + return 0; +} +#endif diff --git a/arm_mps2_an386_clang/liteos_m/board/include/soc.h b/arm_mps2_an386_clang/liteos_m/board/include/soc.h new file mode 100644 index 0000000000000000000000000000000000000000..d4e0391998134b20b79a45d2a81c51caa677ef11 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/include/soc.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ST_CONFIG_H +#define _ST_CONFIG_H + +#define IRQn_Type int + +#define __CM4_REV 0x0001 +#define __NVIC_PRIO_BITS 4 +#define __MPU_PRESENT 1 +#define __Vendor_SysTickConfig 0 +#define __FPU_PRESENT 1 + +#define SysTick_IRQn (-1) +#define PendSV_IRQn (-2) +#define NonMaskableInt_IRQn (-14) +#define MemoryManagement_IRQn (-12) +#define BusFault_IRQn (-11) +#define UsageFault_IRQn (-10) +#define SVCall_IRQn (-5) + +#define Uart0_Rx_IRQn 0 + +#define SYSCLK_FREQ 25000000 + +#define UART0_BASE 0x40004000 +#define UART1_BASE 0x40005000 +#define UART2_BASE 0x40006000 +#define UART3_BASE 0x40007000 +#define UART4_BASE 0x40009000 + +#define UART0_CLK_FREQ SYSCLK_FREQ +#define UART0_BAUDRAT 115200 + +#define WATCHDOG_BASE 0x40008000 +#define GPIO_BASE(no) (0x40010000 + (unsigned int)(no) * 0x1000) /* no: 0 ~ 3 */ +#define TIMER_BASE(no) (0x40000000 + (unsigned int)(no) * 0x1000) + +#endif + +#include "core_cm4.h" diff --git a/arm_mps2_an386_clang/liteos_m/board/include/uart.h b/arm_mps2_an386_clang/liteos_m/board/include/uart.h new file mode 100644 index 0000000000000000000000000000000000000000..7313cb5936f2950d72792eec79c6d46bcc9e4d99 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/include/uart.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _UART_H +#define _UART_H + +#include "los_event.h" +#include "los_compiler.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +extern VOID UartInit(VOID); +extern INT32 UartPutc(INT32 c, VOID *file); +extern INT32 UartGetc(VOID); +extern VOID Uart0RxIrqRegister(VOID); + +extern EVENT_CB_S g_shellInputEvent; + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ +#endif diff --git a/arm_mps2_an386_clang/liteos_m/board/libc/dprintf.c b/arm_mps2_an386_clang/liteos_m/board/libc/dprintf.c new file mode 100644 index 0000000000000000000000000000000000000000..32e1997fbda6f5de8478b23324dd74f35cde4ddc --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/libc/dprintf.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "securec.h" +#include "uart.h" +#include "los_debug.h" +#include "los_interrupt.h" + +static void dputs(char const *s, int (*pFputc)(int n, FILE *cookie), void *cookie) +{ + unsigned int intSave; + + intSave = LOS_IntLock(); + while (*s) { + pFputc(*s++, cookie); + } + LOS_IntRestore(intSave); +} + +int printf(char const *fmt, ...) +{ +#define BUFSIZE 256 + char buf[BUFSIZE] = { 0 }; + va_list ap; + va_start(ap, fmt); + int len = vsnprintf_s(buf, sizeof(buf), BUFSIZE - 1, fmt, ap); + va_end(ap); + if (len > 0) { + dputs(buf, UartPutc, 0); + } else { + dputs("printf error!\n", UartPutc, 0); + } + return len; +} diff --git a/arm_mps2_an386_clang/liteos_m/board/liteos.ld b/arm_mps2_an386_clang/liteos_m/board/liteos.ld new file mode 100644 index 0000000000000000000000000000000000000000..27e38076e31d7d8cf41ae896782d6fababb347bb --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/liteos.ld @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Vector_Table) + +SVC_IRQ_STACK_SIZE = 4K; +FLASH_START = 0x00000000; +FLASH_SIZE = 3M; +PS_RAM_START = 0x21000000; +PS_RAM_SIZE = 16M; + +MEMORY +{ + flash(rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE + ram(rwx) : ORIGIN = PS_RAM_START, LENGTH = PS_RAM_SIZE +} + +SECTIONS +{ + _stext = .; + .vector : { + KEEP (*(SORT_NONE(.Vector_Table))) + } > flash + + .got : { + *(.got.plt) + *(.igot.plt) + *(.got) + *(.igot) + } > flash + + .text : { + . = ALIGN(0x4); + __text_start = .; + *(.text.*) + . = ALIGN(0x4); + _etext = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + } > ram + + .data : { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + } > ram + + .bss : ALIGN(0x4) { + __bss_start = .; + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(0x4); + __bss_end = .; + } > ram + + _sstack = .; + .stack : ALIGN(0x8) { + _stack = .; + __irq_stack_bootom = .; + . += SVC_IRQ_STACK_SIZE; + __irq_stack_top = .; + _estack = .; + } > ram + + .heap (NOLOAD): ALIGN(0x40) { + __heap_start = .; + } > ram + + __heap_size = PS_RAM_SIZE - (__heap_start - __text_start); + end = .; + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } +} diff --git a/arm_mps2_an386_clang/liteos_m/board/main.c b/arm_mps2_an386_clang/liteos_m/board/main.c new file mode 100644 index 0000000000000000000000000000000000000000..2e4e73433bec47d91f004cc20a3ef6f5af482374 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/main.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "los_config.h" +#include "uart.h" +#include "los_debug.h" +#include "lan9118_eth_drv.h" + + +unsigned int LosAppInit(VOID); +extern unsigned int LosShellInit(void); +/***************************************************************************** + Function : main + Description : Main function entry + Input : None + Output : None + Return : None + *****************************************************************************/ +LITE_OS_SEC_TEXT_INIT int main(void) +{ + unsigned int ret; + + UartInit(); + + ret = LOS_KernelInit(); + if (ret != LOS_OK) { + printf("LiteOS kernel init failed! ERROR: 0x%x\n", ret); + goto EXIT; + } +#if (LOSCFG_SUPPORT_LITTLEFS == 1) + LfsLowLevelInit(); +#endif + + Uart0RxIrqRegister(); + + NetInit(); + +#if (LOSCFG_USE_SHELL == 1) + ret = LosShellInit(); + if (ret != LOS_OK) { + printf("LosAppInit failed! ERROR: 0x%x\n", ret); + } +#endif + + ret = LosAppInit(); + if (ret != LOS_OK) { + printf("LosAppInit failed! ERROR: 0x%x\n", ret); + } + + LOS_Start(); + +EXIT: + while (1) { + __asm volatile("wfi"); + } +} diff --git a/arm_mps2_an386_clang/liteos_m/board/startup.s b/arm_mps2_an386_clang/liteos_m/board/startup.s new file mode 100644 index 0000000000000000000000000000000000000000..4ce1a50f2b62f651de70cf6883c9da3060628b18 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/startup.s @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.extern HalExcNMI; +.extern HalExcHardFault; +.extern HalExcMemFault; +.extern HalExcBusFault; +.extern HalExcUsageFault; +.extern HalExcSvcCall; +.extern HalPendSV; +.extern SysTick_Handler; +.global Vector_Table +.global Reset_Handler + +.section .text +.type Reset_Handler, %function +Reset_Handler: + ldr r0, =__bss_start + ldr r1, =__bss_end + mov r2, #0 + +bss_loop: + str r2, [r0, #0] + add r0, r0, #4 + subs r3, r1, r0 + bne bss_loop + + ldr sp, =__irq_stack_top + b main +.size Reset_Handler, .-Reset_Handler + +.type DefaultHandler, %function +DefaultHandler: +loop: + b loop +.size DefaultHandler, .-DefaultHandler + +.section .Vector_Table,"a",%progbits +.type Vector_Table, %object +Vector_Table: + .word _estack + .word Reset_Handler + .word HalExcNMI + .word HalExcHardFault + .word HalExcMemFault + .word HalExcBusFault + .word HalExcUsageFault + .word 0 + .word 0 + .word 0 + .word 0 + .word DefaultHandler + .word DefaultHandler + .word 0 + .word HalPendSV + .word SysTick_Handler + +.size Vector_Table, .-Vector_Table diff --git a/arm_mps2_an386_clang/liteos_m/board/target_config.h b/arm_mps2_an386_clang/liteos_m/board/target_config.h new file mode 100644 index 0000000000000000000000000000000000000000..2a151287b5a934cecd390cb92b783a56f4d4b444 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/target_config.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**@defgroup los_config System configuration items + * @ingroup kernel + */ + +#include "soc.h" +#include "stdbool.h" + +#ifndef _TARGET_CONFIG_H +#define _TARGET_CONFIG_H + +/*============================================================================= + System clock module configuration +=============================================================================*/ +#define OS_SYS_CLOCK SYSCLK_FREQ +#define LOSCFG_BASE_CORE_TICK_PER_SECOND (100UL) +#define LOSCFG_BASE_CORE_TICK_HW_TIME 0 +#define LOSCFG_BASE_CORE_TICK_WTIMER 0 +#define LOSCFG_BASE_CORE_TICK_RESPONSE_MAX 0xFFFFFFUL + +/*============================================================================= + Hardware interrupt module configuration +=============================================================================*/ +#define LOSCFG_PLATFORM_HWI 1 +#define LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT 1 +#define LOSCFG_PLATFORM_HWI_LIMIT 128 +/*============================================================================= + Task module configuration +=============================================================================*/ +#define LOSCFG_BASE_CORE_TSK_LIMIT 24 +#define LOSCFG_BASE_CORE_TSK_IDLE_STACK_SIZE (0x500U) +#define LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE (0x1000U) +#define LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE (0x130U) +#define LOSCFG_BASE_CORE_TIMESLICE 1 +#define LOSCFG_BASE_CORE_TIMESLICE_TIMEOUT 20000 +#define LOSCFG_BASE_CORE_TSK_MONITOR 1 +#define LOSCFG_BASE_CORE_EXC_TSK_SWITCH 1 + +/*============================================================================= + Semaphore module configuration +=============================================================================*/ +#define LOSCFG_BASE_IPC_SEM 1 +#define LOSCFG_BASE_IPC_SEM_LIMIT 48 +/*============================================================================= + Mutex module configuration +=============================================================================*/ +#define LOSCFG_BASE_IPC_MUX 1 +#define LOSCFG_BASE_IPC_MUX_LIMIT 24 +/*============================================================================= + Queue module configuration +=============================================================================*/ +#define LOSCFG_BASE_IPC_QUEUE 1 +#define LOSCFG_BASE_IPC_QUEUE_LIMIT 24 +/*============================================================================= + Software timer module configuration +=============================================================================*/ +#define LOSCFG_BASE_CORE_SWTMR 1 +#define LOSCFG_BASE_CORE_SWTMR_ALIGN 1 +#define LOSCFG_BASE_CORE_SWTMR_LIMIT 48 +/*============================================================================= + Memory module configuration +=============================================================================*/ +extern unsigned int __heap_start; +extern unsigned int __heap_size; +#define LOSCFG_SYS_EXTERNAL_HEAP 1 +#define LOSCFG_SYS_HEAP_ADDR (void *)&__heap_start +#define LOSCFG_SYS_HEAP_SIZE (unsigned int)&__heap_size +#define LOSCFG_MEM_MUL_POOL 1 +#define OS_SYS_MEM_NUM 20 +#define LOSCFG_MEM_FREE_BY_TASKID 1 +#define LOSCFG_MEMORY_BESTFIT 1 + +/* ============================================================================= + printf module configuration +============================================================================= */ +#define LOSCFG_KERNEL_PRINTF 1 + +#define LOS_KERNEL_TEST_NOT_SMOKE 0 + +/*============================================================================= + shell module configuration +=============================================================================*/ +#define LOSCFG_USE_SHELL 1 +#define LOSCFG_SHELL_PRIO 3 + +#endif /* _TARGET_CONFIG_H */ diff --git a/arm_mps2_an386_clang/liteos_m/board/test/test_demo.c b/arm_mps2_an386_clang/liteos_m/board/test/test_demo.c new file mode 100644 index 0000000000000000000000000000000000000000..f65103d893aff7f3556b5fccab798d695b29aff3 --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/board/test/test_demo.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "los_task.h" +#include "los_debug.h" + +unsigned int LosAppInit(VOID) +{ + unsigned int ret = LOS_OK; + + return ret; +} diff --git a/arm_mps2_an386_clang/liteos_m/config.gni b/arm_mps2_an386_clang/liteos_m/config.gni new file mode 100644 index 0000000000000000000000000000000000000000..9ae1fc77f861f0334f65b725284c4617cbf2058c --- /dev/null +++ b/arm_mps2_an386_clang/liteos_m/config.gni @@ -0,0 +1,102 @@ +# Copyright (c) 2020-2021 Huawei Device Co., Ltd. +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Kernel type, e.g. "linux", "liteos_a", "liteos_m". +kernel_type = "liteos_m" + +# Kernel version. +kernel_version = "3.0.0" + +# Board CPU type, e.g. "cortex-a7", "riscv32". +board_cpu = "cortex-m4" +target_cpu= "arm" + +# Board arch, e.g. "armv7-a", "rv32imac". +board_arch = "" + +# Toolchain name used for system compiling. +# E.g. gcc-arm-none-eabi, arm-linux-harmonyeabi-gcc, ohos-clang, riscv32-unknown-elf. +# Note: The default toolchain is "ohos-clang". It's not mandatory if you use the default toolchain. +board_toolchain = "ohos-clang" + +use_board_toolchain = true + +# The toolchain path installed, it's not mandatory if you have added toolchain path to your ~/.bashrc. +board_toolchain_path = "" + +# Compiler prefix. +target_triple = "arm-liteos-ohos" +board_toolchain_prefix = "" + +# Compiler type, "gcc" or "clang". +board_toolchain_type = "clang" + +#Debug compiler optimization level options +board_opt_flags = [ + "-O2", +] + +# Board related common compile flags. +board_base_flags = [ + "--target=${target_triple}", + "-mthumb", + "-mcpu=${board_cpu}" +] + +board_cflags = board_base_flags + +board_cflags += [ + "-Wall", + "-fdata-sections", + "-ffunction-sections", + "-fno-builtin", + "-fno-strict-aliasing", + "-fsigned-char", + "-std=c99", + "-DUSE_HAL_DRIVER", + "-D__LITEOS_M__", +] +board_cflags += board_opt_flags + +board_asmflags = [ + "-mcpu=cortex-m4", + "-mthumb", + "-static", +] +board_asmflags += board_opt_flags + +board_cxx_flags = board_cflags + +board_ld_flags = [] + +# Newlib adapt. +board_ld_flags += [ + "-Wl,--wrap=_free_r", + "-Wl,--wrap,_malloc_usable_size_r", + "-Wl,--wrap,_malloc_r", + "-Wl,--wrap,_memalign_r", + "-Wl,--wrap,_realloc_r", + "-Wl,--wrap,_calloc_r", +] + +# Board related headfiles search path. +board_include_dirs = [ "//commonlibrary/utils_lite/include" ] + +# Board adapter dir for OHOS components. +board_adapter_dir = "//device/qemu/arm_mps2_an386_clang/driver" + +# Sysroot path. +board_configed_sysroot = "" + +# Board storage type, it used for file system generation. +storage_type = "spinor" diff --git a/arm_mps2_an386_clang/ohos.build b/arm_mps2_an386_clang/ohos.build new file mode 100644 index 0000000000000000000000000000000000000000..f3301f6f41f0fe80ca602411c2efeb3985c1aaeb --- /dev/null +++ b/arm_mps2_an386_clang/ohos.build @@ -0,0 +1,10 @@ +{ + "parts": { + "device_arm_mps2_an386_clang": { + "module_list": [ + "//device/qemu/arm_mps2_an386_clang:arm_mps2_an386_clang" + ] + } + }, + "subsystem": "device_arm_mps2_an386_clang" +} \ No newline at end of file